PDF AM79C971 Data sheet ( Hoja de datos )

Número de pieza	AM79C971
Descripción	PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
Fabricantes	Advanced Micro Devices
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No Preview Available ! Am79C971 PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus DISTINCTIVE CHARACTERISTICS s Single-chip Fast Ethernet controller for the Peripheral Component Interconnect (PCI) local bus — 32-bit glueless PCI host interface — Supports PCI clock frequency from DC to 33 MHz independent of network clock — Supports network operation with PCI clock from 15 MHz to 33 MHz — High performance bus mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit for low CPU and bus utilization — PCI specification revision 2.1 compliant — Supports PCI Subsystem/Subvendor ID/ Vendor ID programming through the EEPROM interface — Supports both PCI 5.0-V and 3.3-V signaling environments — Plug and Play compatible — Supports an unlimited PCI burst length — Big endian and little endian byte alignments supported s Integrated 10BASE-T and 10BASE-2/5 (AUI) Physical Layer Interface — Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3 and Blue Book Ethernet-compliant solution — Automatic Twisted-Pair receive polarity detection and correction — Internal 10BASE-T transceiver with Smart Squelch to Twisted-Pair medium — IEEE 802.3-compliant auto-negotiable 10BASE-T interface s Supports General Purpose Serial Interface (GPSI) s Media Independent Interface (MII) for connecting external 10- or 100-Megabit per second (Mbps) transceivers — IEEE 802.3-compliant MII — Intelligent Auto-Poll™ external PHY status monitor and interrupt — Includes intelligent on-chip Network Port Manager that provides auto-port selection between MII, on-chip 10BASE-T port, and AUI without software support — Supports both auto-negotiable and non auto-negotiable external PHYs — Supports 10BASE-T, 100BASE-TX/FX, 100BASE-T4, and 100BASE-T2 IEEE 802.3- compliant MII PHYs at full- or half-duplex s Internal/external loopback capabilities on all ports s Supports patented External Address Detection Interface (EADI) — Receive frame tagging support for inter- networking applications s Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 and Blue Book Ethernet standards s Full-duplex operation supported in AUI, 10BASE-T, MII, and GPSI ports with independent Transmit (TX) and Receive (RX) channels s Flexible buffer architecture — Large independent internal TX and RX FIFOs — SRAM-based FIFO buffer extension supporting up to 128 kilobytes (Kbytes) — 1/2 Gigabit per second (Gbps) internal data bandwidth — Programmable FIFO watermarks for both TX and RX operations — RX frame queuing for high latency PCI bus host operation — Programmable allocation of buffer space between RX and TX queues s EEPROM interface supports jumperless design and provides through-chip programming — Supports full programmability of half-/full- duplex operation for external 100 Mbps PHYs through EEPROM mapping s Extensive LED status support Publication# 20550 Rev: E Amendment: /0 Issue Date: May 2000 1 page BLOCK DIAGRAM CLK RST AD[31:00] C/BE[3:0] PAR FRAME TRDY IRDY STOP IDSEL DEVSEL REQ GNT PERR SERR INTA SLEEP TCK TMS TDI TDO EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS ERAMCS AS_EBOE EBWE EBCLK Expansion Bus Interface GPSI Port PCI Bus Interface Unit Bus Rcv FIFO MAC Rcv FIFO Bus Xmt FIFO MAC Xmt FIFO Buffer Management Unit JTAG Port Control FIFO Control Network Port Manager Auto Negotiation MII Port 802.3 MAC Core EADI Port Manchester Encoder/ Decoder (PLS) & AUI Port 10BASE-T MAU 93C46 EEPROM Interface LED Control TXEN TXCLK TXDAT RXEN RXCLK RXDAT CLSN TX_E TXD[3:0] TX_EN TX_CLK COL RXD[3:0] RX_ER RX_CLK RX_DV CRS MDC MDIO SRDCLK SRD SF/BD EAR RXFRTGD/MIIRXFRTGD RXFRTGE/MIIRXFRTGE XTAL1 XTAL2 DO+/- DI+/- CI+/- TXD+/- TXP+/- RXD+/- EECS EESK EEDI EEDO LED0 LED1 LED2 LED3 20550D-1 Am79C971 5 5 Page CONNECTION DIAGRAM (PQR160) IDSEL VDD AD23 AD22 VSS AD21 AD20 VDD_PCI AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP VSSB PERR SERR VDD_PCI PAR C/BE1 AD15 AD14 AD13 AD12 VSSB AD11 AD10 VDD AD9 AD8 VSS C/BE0 AD7 AD6 VSSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PCnet™-FAST AmA7m9C7997C19K7C1/W Pin 1 is marked for orientation. 120 XTAL2 119 VSS_PLL 118 XTAL1 117 AVDDB 116 TXD+ 115 TXP+ 114 TXD- 113 TXP- 112 AVDDB 111 RXD+ 110 RXD- 109 VSS 108 MDIO 107 MDC 106 SLEEP/EAR 105 RXD3 104 RXD2 103 RXD1 102 RXD0/RXFRTGD 101 VDDB 100 RX_DV/RXFRTGE 99 RX_CLK/RXCLK 98 RX_ER/RXDAT 97 VSSB 96 TX_ER 95 TX_CLK/TXCLK 94 TX_EN/TXEN 93 VDDB 92 TXD0/TXDAT 91 TXD1 90 TXD2 89 TXD3 88 COL/CLSN 87 CRS/RXEN 86 VSSB 85 EBD0 84 EBD1 83 EBD2 82 EBD3 81 EBD4 2055A-2 20550D-2 Am79C971 11 11 Page

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