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PDF CY4617 Data sheet ( Hoja de datos )
| Número de pieza | CY4617 | |
| Descripción | ISD-300LP Low-Power USB 2.0 to ATA/ATAPI Bridge IC | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C68310
ISD-300LP™ Low-Power USB 2.0 to ATA/ATAPI Bridge IC
1.0 Features
• Fixed-function mass storage device–requires no firmware
code
• USB Mass Storage Class Bulk-Only specification-compliant
(version 1.0)
• USB 2.0-certified (TID# 40001426)
• Integrated USB transceiver
• High-speed (480-Mbit) and full-speed (12-Mbit) support
• USB Suspend/Resume, Remote Wakeup support
• Two power modes of operation–self-powered and USB bus-
powered
• Low power consumption allows for bus-powered opera-
tion
• VBUS-powered CF support
• True USB portable HDD support
• Compact 80-pin TQFP package with a Lead-Free option
• ATA/ATAPI-6 specification-compliant–provides support for
mass storage devices larger than 137GB
• 5V tolerant inputs, 3.3V output drive
• Flexible USB descriptor and configuration retrieval sources
• I2C-compatible serial ROM interface
• ATA interface using vendor-specific ATA command (FBh)
implemented on ATAPI or ATA device
• Default on-chip ROM contents for manufacturing/devel-
opment
• 2-Kbyte SRAM data buffer for ATA/ATAPI data transfers
• ATA interface supports ATA PIO modes 0–4, UDMA modes
0–4 (multiword DMA not supported). ATA interface
operation mode is automatically selected during device
initialization or manually programmed with I2C-compatible
configuration data
• Automatic detection of either Master or Slave ATA/ATAPI
devices
• Mode Page 5 Support–increased support for formatting
removable media devices
• ATA Interrupt support for ATAPI devices–offers more robust
ATA support across OS platforms
• System event notification via Vendor-specific ATA
command
• Input pin for media cartridge detection or ejection request
• USB bus state indications (Reset, FS/HS mode of oper-
ation, Suspend/Resume, Bus/Self-powered)
• Three General Purpose I/O (GPIO) pins
• Multiple LUNs supported within a single ATAPI device
• ATA translation provides seamless ATA support with
standard MSC drivers
• Additional ATA command support provided by vendor-
specific ATACBs (ATA command blocks utilizing the MSC
Command Block Wrapper)
• Provisions to share ATA bus with other hosts (e.g.
USB/1394 dual device)
• Manufacturing interconnect test support provided with
vendor-specific USB commands:
• Read/Write access to relevant ASIC pins
• Manufacturing Interconnect Test Tools
• Utilizes inexpensive 30-Mhz crystal for clock source.
1.1 Functional Block Diagram
USB HS/FS
Control Logic
nEJECT
SYSIRQ
DRVPWRVLD
DISKRDY
GPIO Pins (3)
CY7C68310
Control Logic
USB
2.0
Xcvr
VBUS
D+
D-
OSC
LOWPWR
nPWR500
VBUSPWRVLD
VBUSPWRD
nRESET
SCL
SDA
ROM
EEPROM
Interface
Control
64 Byte
RAM
2kByte FIFO
ATA Interface Logic
ATAEN
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document 38-08030 Rev. *H
• 3901 North First Street
• San Jose, CA 95134 • 408-943-2600
Revised June 28, 2004
1 page  
CY7C68310
4.3 Detailed Pin Descriptions
4.3.1 DP, DM
DP and DM are the high-speed USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB. See section 15.0 for PCB layout guidelines.
4.3.2 RSDP, RSDM
RSDP and RSDM are the full-speed USB signaling pins, and
they should be tied to the DP and DM pins through 39Ω
resistors. RSDP and RSDM also function as current sinks for
termination during high-speed operation.
4.3.3 TEST[0:3]
The test pins control the various test modes of the
CY7C68310. Most test modes are reserved for ASIC fabri-
cation, but the following table outlines the test modes available
for device manufacturing environments. The test pins must be
tied to GND for normal operation.
Table 4-1. CY7C68310 Test Modes
Test Mode
Description
0000 Normal Mode. This is the default mode of operation.
0001 Reserved.
0010
Limbo Mode. All output pins set to high-Z during Limbo mode operation with the exception of the XO pin. The XO
pin output cell does not have high-Z control (always enabled), and must be disabled or disconnected by other
means. To enter Limbo Mode, nRESET must be toggled after the Test pins are set to ‘0010’.
0011
Input xnorTree Mode. This mode tests the connectivity of all dedicated inputs and outputs. While in the Input
xnorTree Mode of operation, all bi-directional pins are wired as chain outputs. The results of the connectivity
procedure will be seen on all bidirectional pins. Chain Inputs (in order): VBUSPWRVLD, VBUSPWRD, DISKRDY,
ATAIRQ, IORDY, DMARQ, nRESET, ATAEN, DRVPWRVLD, SYSIRQ, nEJECT Chain Outputs (in order):
GPIO[2:0], DD[15:0], SDA_nIMODE.
0100
Bi-di xnorTree Mode. This mode test the connectivity of all bi-directional inputs. While in the Bi-di xnor Tree Mode
of operation, all bi-directional pins are wired as inputs and become part of the xnor Tree chain. The results of the
connectivity procedure will be seen on all output only pins. Chain Inputs: GPIO[0], GPIO[1], GPIO[2], DD[7], DD[8],
DD[6], DD[0], DD[5], DD[10], DD[4], DD[11], DD[3], DD[12], DD[2], DD[13], DD[1], DD[14], DD[0], DD[15],
SDA_nIMODE. Chain Outputs: nPWR500, nATARST, nDIOW, nDIOR, nDMACK, ATAPUEN, nCS[1:0], DA[2:0],
LOWPWR, SCL
0101–1111 Reserved.
4.3.4 XI, XO
The CY7C68310 requires a 30-MHz signal to derive internal
timing. Typically a 30-MHz (2.5V tolerant, parallel-resonant
fundamental mode) crystal is used, but a 30-MHz (2.5V, 50%
duty cycle) square wave from another source can also be
used. If a crystal is used, connect the pins to XI and XO, and
also through 20pF capacitors to GND as shown in Figure 8-1.
If an alternate clock source is used, apply it to XI and leave XO
open.
4.3.5 nEJECT
The nEJECT input pin provides a means to communicate an
Eject button push to the ATA/ATAPI device via event notifi-
cation as well as a way to cause a USB Remote-wakeup.
During normal operation, asserting nEJECT for 10ms
indicates that a media eject has been requested. If the
CY7C68310 is in a suspend state, and if remote wakeup is
enabled by the USB host, a state change on this pin will
immediately cause the CY7C68310 to perform a USB remote
wakeup event.
4.3.6 SYSIRQ
The SYSIRQ pin provides a way for systems to request service
from host software by use of the USB Interrupt pipe. If the
CY7C68310 has no pending interrupt data to return, USB
interrupt pipe data requests are NAKed. If pending data is
available, CY7C68310 returns 16 bits of data indicating the
state of the DISKRDY pin, the HS_MODE signal (that
indicates whether CY7C68310 is operating in high-speed or
full-speed), the VBUSPWRD pin, the User-Defined values
from bits [7:3] of address 0xE of the configuration space, and
the GPIO Pins. Table 4-2 shows the bitmap for the data
returned on the interrupt pipe, and the figure beneath it depicts
the latching algorithm incorporated by CY7C68310.
Document 38-08030 Rev. *H
Page 5 of 34
5 Page 
CY7C68310
Table 5-2. ATACB2 Field Descriptions
Byte
4
5
6-15
Field Name
Field Description
Bit 1 DeviceSelectionOverride - This bit determines when the device selection
will be performed in relation to the command register write accesses.
0 = Device selection will be performed prior to command register accesses
1 = Device selection will be performed following command register accesses
Bit 0 TaskFileRead - This bit determines whether or not the taskfile register data
selected in bmATACB2RegisterSelect is returned. If this bit is set, the
dCBWDataTransferLength field must be set to 12.
0 = Execute ATACB2 command and data transfer (if any)
1 = Only read taskfile registers selected in bmATACBRegisterSelect and return
0x00h for all others. The format of the 12 bytes of returned data is as follows:
• Address offset 0x00h (3F6h) Alternate Status (HOB=0)
• Address offset 0x01h (1F6h) Device / Head (HOB=0)
• Address offset 0x02h (1F1h) Error (HOB=0)
• Address offset 0x03h (1F2h-M) Sector Count (HOB=1)
• Address offset 0x04h (1F3h-M) LBA Low (Sector Number) (HOB=1)
• Address offset 0x05h (1F4h-M) LBA Mid (Cylinder Low) (HOB=1)
• Address offset 0x06h (1F5h-M) LBA High (Cylinder High) (HOB=1)
• Address offset 0x07h (1F2h-L) Sector Count (HOB=0)
• Address offset 0x08h (1F3h-L) LBA Low (HOB=0)
• Address offset 0x09h (1F4h-L) LBA Mid (HOB=0)
• Address offset 0x0Ah (1F5h-L) LBA High (HOB=0)
• Address offset 0x0Bh (1F7h) Status (HOB=0)
bATACB2TransferBlockCount[7:4] These bits indicate the DRQ block size in 512-byte increments. This value is log
base 2 of the block size. Legal values are 0 (1 sector per block) through 8 (256
sectors per block). A command failed status will be returned if an illegal value
is used in the ATACB2. For commands using multiple sector PIO data transfers,
the number of sectors per block must equal the current Multiple Sector Setting
of the drive. These bits should be set to ‘0’ for non-multiple, non-UDMA
commands.
bmATACB2ActionSelect2[3:0] This field controls the execution of the ATACB according to the bitfield values:
Bits 3-1 Reserved - These bits must be set to ‘0’
Bit 0 48-bit-write - Determines whether or not M data is used to read 1F2-1F5
0 = Do not read or write 1F2-1F5 with “-M” data
1 = Read or write 1F2-1F5 with “-M” data
bATACB2DeviceHeadData
The contents of this field are used for writing the Device Head register when
Byte 2, Bit 6 of the ATACB2 is set to ‘1’. Otherwise, the value written will be
determined by the bridge.
Bits 7-5 DevHead - Data used to write to Device Head register.
Bit 4 DEVOverride - This bit reflects the state of Byte 3, Bit 5 of the ATACB2.
Bits 3-0 DevHead - Data used to write to Device head register.
bATACB2TaskFileWriteData
These bytes contain ATA register data used with ATA command or PIO write
operations. Only registers selected in bmATACB2RegisterSelect are required
to hold valid data when accessed. The registers are as follows:
• ATACB2 Address offset 6h (1F1h) Features
• ATACB2 Address offset 7h (1F2h-M) Sector Count
• ATACB2 Address offset 8h (1F3h-M) LBA Low (Sector Number)
• ATACB2 Address offset 9h(1F4h-M) LBA Mid (Cylinder Low)
• ATACB2 Address offset Ah (1F5h-M) LBA High (Cylinder High)
• ATACB2 Address offset Bh (1F2h-L) Sector Count
• ATACB2 Address offset Ch (1F3h-L) LBA Low
• ATACB2 Address offset Dh (1F4h-L) LBA Mid
• ATACB2 Address offset Eh (1F5h-L) LBA High
• ATACB2 Address offset Fh (1F7h) Command
Document 38-08030 Rev. *H
Page 11 of 34
11 Page | ||
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