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PDF CXP88860 Data sheet ( Hoja de datos )
| Número de pieza | CXP88860 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP88852/88860
CMOS 8-bit Single Chip Microcomputer
Description
The CXP88852/88860 is a CMOS 8-bit micro-
computer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuits, PWM
output, VISS/ VASS circuit, 32kHz timer/counter,
remote control receiving circuit, VSYNC separator
and the measurement circuit which measure signals
of capstan FG amplifier and drum FG/PG amplifier
and other servo systems, as well as basic
configurations like 8-bit CPU, ROM, RAM and I/O
port. They are integrated into a single chip.
Also, CXP88852/88860 provides sleep/stop function
which enables to lower power consumption.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity 52K bytes (CXP88852)
60K bytes (CXP88860)
• Incorporated RAM capacity 1600 bytes (including PPG RAM)
• Peripheral function
— A/D converter
8 bits, 14 channels, successive approximation system
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO for data
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
— Timer
8-bit timer/counter, 2 channels
19-bit time base timer
32kHz timer/counter
— High precision timing pattern generation PPG 19 pins 32-stage programmable circuit
RTG 5 pins, 1 channel
5-bit, 8-satge FIFO (RECCTL control), 1channel
— PWM/DA gate output
12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse output, 13 bits, 2 channels
— Analog signal input circuit
Capstan FG amplifier circuit
Drum FG amplifier circuit
Drum PG amplifier circuit
PBCTL amplifier circuit
— CTL write/rewrite circuit
Recording current control circuit
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1 channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— 32kHz timer/event counter
32kHz oscillation circuit, ultra-low speed instruction mode
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— Tri-state output
PPG 1 pin, output 8 pins
— Pseudo HSYNC output function
— High speed head switching circuit
• Interruption
20 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP88800 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96515-ST
1 page  
CXP88852/88860
Description
I/O
AN0/ANOUT Input/Output
AN1 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
Input
Input/Input
Output/Input
PG0/AN12
PG1/AN13
Input/Input
PH0 to PH7 Output
PI0/INT0
I/O/Input
PI1/EC/
INT2
I/O/Input/Input
PI2 to PI7
CFG
DFG
DPG
RECCTL (+)
RECCTL (–)
CTLCIN (+)
CTLCIN (–)
CTLAMP (+)
CTLAMP (–)
CTLFAMPO
CTLSAMPI
RECCAP
I/O
Input
Input
Input
I/O
Output
Input
Output
Input
I/O
VREFOUT
CTLAG
AMPVSS
AMPVDD
Output
Output
Description
Analog circuit internal
waveform output pin.
(Port F)
Lower 4 bits are for inputs; upper 4 bits are for
outputs. Lower 4 bits are standby release input
pins.
(8 pins)
Analog input pin for
A/D converter.
(14 pins)
(Port G)
2-bit input port.
(2 pins)
(Port H)
8-bit output port; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
(Port I)
8-bit I/O port. I/O can be
set in a unit of single bits.
Function as standby
release input can be set in
a unit of single bits.
(8 pins)
Input pin to request external interruption.
Active when falling edge.
Input pin to request
External event input external interruption.
pin for timer/counter. Active when falling
edge.
Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
RECCTL signal output pin.
(2 pins)
PBCTL signal input pin.
(2 pins)
Connected to RECCTL (+) and RECCTL (–) with the internal switch for
playback. (2 pins)
Input PBCTL signal with capacitor coupled.
(2 pins)
PBCTL signal 1st amplifier output.
PBCTL signal 2nd amplifier input.
Capacitor connecting pin for the slope setting of the CTL writing
trapezoidal wave.
Capacitor connecting pin for the VREF level smoothing of DPG, DFG
and CFG.
Capacitor connecting pin for the CTL and AGND smoothing.
Analog signal input circuit GND pin.
Analog signal input circuit power supply pin.
–5–
5 Page 
Pin
PG0/AN12
to
PG1/AN13
Port G
Circuit format
Input multiplexer
IP A/D converter
2 pins
PH0
to
PH7
8 pins
Port H
Data bus
RD (Port G)
Medium drive
voltage12 V
Port H data
Data bus
Port I
RD (Port H)
Port I data
Large current 12mA
PI0/INT0
to
PI1/EC/INT2
2 pins
PI2
to
PI7
6 pins
Port I direction
Data bus
RD (Port I)
Edge detection
Standby release
Interruption circuit
Data bus
Port I
RD (Port I direction)
Port I data
Port I direction
Data bus
RD (Port I)
Edge detection
Standby release
Data bus
RD (Port I direction)
IP
IP
CXP88852/88860
When reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXP88860.PDF ] | |
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