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HM-6561883 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HM-6561883
Beschreibung 256 x 4 CMOS RAM
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
HM-6561883 Datasheet, Funktion
HM-6561/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
The HM-6561/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high per-
formance and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
• Three-State Output
• Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERATURE RANGE
220ns
CERDIP
-55oC to +125oC
HM1-6561B/883
300ns
HM1-6561/883
PKG. NO.
F18.3
Pinout
HM-6561/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
E9
18 VCC
17 A4
16 W
15 S1
14 DQ3
13 DQ2
12 DQ1
11 DQ0
10 S2
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
DQ Data In/Out
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-117
File Number 2990.1






HM-6561883 Datasheet, Funktion
HM-6561/883
Timing Waveforms
(7) TAVEL
(8)
TELAX
(7) TAVEL
A VALID
(6) TEHEL
E
(17) TELEL
(5) TELEH
(6) TEHEL
HIGH
W
DQ PREVIOUS DATA
(4)
TSHQZ
S1, S2
HIGH Z
(1) TELQV
(2) TAVQV
(4)
TSLQX
VALID DATA LATCHED
(4)
TSHQZ
HIGH Z
TIME
REFERENCE
-1 0
1
FIGURE 1. READ CYCLE
2
3
45
TRUTH TABLE
TIME
REFERENCE
E
INPUTS
S1 W
OUTPUT
A DQ
FUNCTION
-1 H H X X Z Memory Disabled
0
XHV
Z Cycle Begins, Addresses are Latched
1 L L H X X Output Enabled
2 L L H X V Output Valid
3
LHX
V Output Latched
4 H H X X Z Device Disabled, Prepare for Next Cycle (Same as -1)
5
XHV
Z Cycle Ends, Next Cycle Begins (Same as 0)
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The HM-6561/883 Read Cycle is initiated on the falling edge
of E. This signal latches the input address word into on-chip
registers. Minimum address setup and hold times must be
met. After the required hold time, the address lines may
change state without affecting device operation. In order to
read the output data E, S1 and S2 must be low and W must
be high. The output data will be valid at access time
(TELQV).
The HM-6561/883 has output data latches that are con-
trolled by E. On the rising edge of E the present data is
latched and remains latched until E falls. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.
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