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HM-6551883 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HM-6551883
Beschreibung 256 x 4 CMOS RAM
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
HM-6551883 Datasheet, Funktion
HM-6551/883
March 1997
256 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous cir-
cuit design techniques are employed to achieve high perfor-
mance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be main-
tained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE
CERDIP
TEMPERATURE RANGE
220ns
-55oC to +125oC
HM-6551B/883
300ns
HM1-6551/883
PKG. NO.
F22.4
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
D0 9
Q0 10
D1 11
22 VCC
21 A4
20 W
19 S1
18 E
17 S2
16 Q3
15 D3
14 Q2
13 D2
12 Q1
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-101
File Number 2988.1






HM-6551883 Datasheet, Funktion
Timing Waveforms
(8) TAVEL
A
(7) TEHEL
E
(9) TS2LEL
S2
HM-6551/883
(10)
TELAX
VALID
TELS2X
(11)
(19) TELEL
TELEH (6)
(8) TAVEL
NEXT
TEHEL (7)
(9) TS2LEL
D
Q
S1
W
TIME
REFERENCE
HIGH
TELQV (1)
TAVQV (2)
(3) TS1LQX
VALID OUTPUT
-1 0
12
FIGURE 1. READ CYCLE
3
TS1HQZ (5)
45
TIME
REFERENCE
-1
0
1
2
3
4
5
E
H
L
L
H
TRUTH TABLE
INPUTS
OUTPUTS
S1 S2 W A D
Q
FUNCTION
HXXXX
Z Memory Disabled
X L HVX
Z Addresses and S2 are Latched,
Cycle Begins
L XHXX
X Output Enabled but Undefined
L XHXX
V Data Output Valid
L XHXX
V Outputs Latched, Valid Data,
S2 Unlatches
HXXXX
Z Prepare for Next Cycle
(Same as -1)
X L HVX
Z Cycle Ends, Next Cycle Begins
(Same as 0)
The HM-6551/883 Read Cycle is initiated by the falling edge
of E. This signal latches the input address word and S2 into
on-chip registers providing the minimum setup and hold
times are met. After the required hold time, these inputs may
change state without affecting device operation. S2 acts as a
high order address and simplifies decoding. For the output to
be read, E, S1 must be low and W must be high. S2 must
have been latched low on the falling edge of E. The output
data will be valid at access time (TELQV). The HM-6551/883
has output data latches that are controlled by E. On the ris-
ing edge of E the present data is latched and remains in that
state until E falls. Also on the rising edge of E, S2 unlatches
and controls the outputs along with S1. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.
6-106

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