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HM-6504883 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HM-6504883
Beschreibung 4096 x 1 CMOS RAM
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 10 Seiten
HM-6504883 Datasheet, Funktion
HM-6504/883
March 1997
4096 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high perfor-
mance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
PACKAGE TEMPERATURE RANGE
200ns
CERDIP
-55oC to +125oC
HM1-6504B/883
300ns
HM1-6504/883
PKG. NO
F18.3
Pinout
HM-6504/883 (CERDIP)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
Q7
W8
GND 9
18 VCC
17 A6
16 A7
15 A8
14 A9
13 A10
12 A11
11 D
10 E
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-134
File Number 2993.1






HM-6504883 Datasheet, Funktion
HM-6504/883
Timing Waveforms
(8)
(7) TELAX
TAVEL
A ADD VALID
(6)
TEHEL
E
(1) TELQV
(3)
HIGH Z
TELQX
Q
TELEL (18)
TELEH
(5)
(4) TEHQZ
VALID DATA OUTPUT
W
TIME
REFERENCE
HIGH
-1 0
1
2
FIGURE 1. READ CYCLE
(7)
TAVEL
NEXT ADD
TEHEL
(6)
HIGH Z
34
5
TRUTH TABLE
INPUTS
OUTPUT
TIME REFERENCE
E
W
A
Q
FUNCTION
-1
HXX
Z Memory Disabled
0
HV
Z Cycle Begins, Addresses are Latched
1
LHX
X Output Enabled
2
LHX
V Output Valid
3
HX
V Read Accomplished
4
HXX
Z Prepare for Next Cycle (Same as -1)
5
HV
Z Cycle Ends, Next Cycle Begins (Same as 0)
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
enabled but the data is not valid until during time (T = 2). W
must remain high for the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all input, and ready the RAM for the
next memory cycle (T = 4).
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