Datenblatt-pdf.com


HPC26003 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer HPC26003
Beschreibung High-Performance microControllers
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 36 Seiten
HPC26003 Datasheet, Funktion
PRELIMINARY
April 1994
HPC16083 HPC26083 HPC36083 HPC46083
HPC16003 HPC26003 HPC36003 HPC46003
High-Performance microControllers
General Description
The HPC16083 and HPC16003 are members of the HPCTM
family of High Performance microControllers Each member
of the family has the same core CPU with a unique memory
and I O configuration to suit specific applications The
HPC16083 has 8k bytes of on-chip ROM The HPC16003
has no on-chip ROM and is intended for use with external
direct memory Each part is fabricated in National’s ad-
vanced microCMOS technology This process combined
with an advanced architecture provides fast flexible I O
control efficient data manipulation and high speed compu-
tation
The HPC devices are complete microcomputers on a single
chip All system timing internal logic ROM RAM and I O
are provided on the chip to produce a cost effective solution
for high performance applications On-chip functions such
as UART up to eight 16-bit timers with 4 input capture regis-
ters vectored interrupts WATCHDOGTM logic and MICRO-
WIRE PLUSTM provide a high level of system integration
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typical-
ly performed by microprocessors and expensive peripheral
chips The term ‘‘HPC16083’’ is used throughout this data-
sheet to refer to the HPC16083 and HPC16003 devices un-
less otherwise specified
The microCMOS process results in very low current drain
and enables the user to select the optimum speed power
product for his system The IDLE and HALT modes provide
further current savings The HPC is available in 68-pin
PLCC LDCC PGA and 80-Pin PQFP packages
Features
Y HPC family core features
16-bit architecture both byte and word
16-bit data bus ALU and registers
64k bytes of external direct memory addressing
FAST 200 ns for fastest instruction when using
20 0 MHz clock 134 ns at 30 MHz
High code efficiency most instructions are single
byte
16 x 16 multiply and 32 x 16 divide
Eight vectored interrupt sources
Four 16-bit timer counters with 4 synchronous out-
puts and WATCHDOG logic
MICROWIRE PLUS serial I O interface
CMOS very low power with two power save modes
IDLE and HALT
Y UART full duplex programmable baud rate
Y Four additional 16-bit timer counters with pulse width
modulated outputs
Y Four input capture registers
Y 52 general purpose I O lines (memory mapped)
Y 8k bytes of ROM 256 bytes of RAM on chip
Y ROMless version available (HPC16003)
Y Commercial (0 C to a70 C) industrial (b40 C to
a85 C) automotive (b40 C to a105 C) and military
(b55 C to a125 C) temperature ranges
For applications requiring more RAM and ROM see
HPC16064 data sheet
Block Diagram (HPC16083 with 8k ROM shown)
Series 32000 TapePak and TRI-STATE are registered trademarks of National Semiconductor Corporation
MOLETM HPCTM COPSTM MICROWIRE PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation
UNIX is a registered trademarks of AT T Bell Laboratories
VAXTM is a trademark of Digital Equipment Corporation
IBM and PC AT are registered trademarks of International Business Machines Corporation
SUN is a registered trademark of Sun Microsystems
SunOSTM is a trademark of Sun Microsystems
C1995 National Semiconductor Corporation TL DD 8801
TL DD 8801 – 1
RRD-B30M105 Printed in U S A






HPC26003 Datasheet, Funktion
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 thru Figure 5 ) VCC e 5 0V g10% unless otherwise specified TA e 0 C to a70 C for
HPC46083 HPC46003 b40 C to a85 C for HPC36083 HPC36003 b40 C to a105 C for HPC26083 HPC26003 b55 C to
a125 C for HPC16083 HPC16003 (Continued)
Symbol and Formula
Parameter
Min Max Units
Notes
tDC1ALER
Delay from CKI Rising Edge to ALE Rising Edge
0 35
ns (Notes 1 2)
tDC1ALEF
Delay from CKI Rising Edge to ALE Falling Edge 0 35 ns (Notes 1 2)
tDC2ALER e tC a 20
Delay from CK2 Rising Edge to ALE Rising Edge
37 ns
(Note 2)
tDC2ALEF e tC a 20
Delay from CK2 Falling Edge to ALE Falling Edge
37 ns
(Note 2)
tLL e tC b 9
ALE Pulse Width
24 ns
tST e tC b 7
Setup of Address Valid before ALE Falling Edge
9
ns
tVP e tC b 5
Hold of Address Valid after ALE Falling Edge
11
ns
tARR e tC b 5
ALE Falling Edge to RD Falling Edge
12 ns
tACC e tC a WS b 32
Data Input Valid after Address Output Valid
100 ns
(Note 6)
tRD e tC a WS b 39
Data Input Valid after RD Falling Edge
60 ns
tRW e tC a WS b 14
RD Pulse Width
85 ns
tDR e tC b 15
Hold of Data Input Valid after RD Rising Edge
0 35 ns
tRDA e tC b 15
Bus Enable after RD Rising Edge
51 ns
tARW e tC b 5
ALE Falling Edge to WR Falling Edge
28 ns
tWW e tC a WS b 15 WR Pulse Width
101 ns
tV e tC a WS b 5
Data Output Valid before WR Rising Edge
94
ns
tHW e tC b 10
Hold of Data Valid after WR Rising Edge
7
ns
tDAR e tC a WS b 50
tRWP e tC
Falling Edge of ALE to Falling Edge of RDY
RDY Pulse Width
33
66
ns
ns
Note CL e 40 pF
Note 1 These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO wih rise and fall
times (tCKIR and tCKIL) on CKI input less than 2 5 ns
Note 2 Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3 tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later tHAE as long as (3tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input
Note 4 WS tWAIT c (number of pre-programmed wait states) Minimum and maximum values are calculated from maximum operating frequency tC e 30 MHz
with one wait state programmed
Note 5 Due to emulation restrictions actual limits will be better
Note 6 This is guaranteed by design and not tested
CKI Input Signal Characteristics
Rise Fall Time
Duty Cycle
TL DD 8801–35
FIGURE 1 CKI Input Signal
TL DD 8801 – 36
FIGURE 2 Input and Output for AC Tests
TL DD 8801 – 38
Note AC testing inputs are driven at VIH for a logic ‘‘1’’ and VIL for a logic ‘‘0’’ Output timing measurements are made at 2 0V for a logic ‘‘1’’ and 0 8V for a logic
‘‘0’’
6

6 Page









HPC26003 pdf, datenblatt
Pin Descriptions (Continued)
B14 TS3
Timer Synchronous Output
B15 RDRDY Read Ready Output for UPI Mode
When accessing external memory four bits of port B
are used as follows
B10 ALE
B11 WR
B12 HBE
B15 RD
Address Latch Enable Output
Write Output
High Byte Enable Output Input
(sampled at reset)
Read Output
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions
I0
I1 NMI
I2 INT2
I3 INT3
I4 INT4
I5 SI
I6 RDX
I7
Nonmaskable Interrupt Input
Maskable Interrupt Input Capture URD
Maskable Interrupt Input Capture UWR
Maskable Interrupt Input Capture
MICROWIRE PLUS Data Input
UART Data Input
Port D is an 8-bit input port that can be used as general
purpose digital inputs
Port P is a 4-bit output port that can be used as general
purpose data or selected to be controlled by timers 4
through 7 in order to generate frequency duty cycle and
pulse width modulated outputs
POWER SUPPLY PINS
VCC1 and
VCC2
Positive Power Supply
GND
Ground for On-Chip Logic
DGND Ground for Output Buffers
Note There are two electrically connected VCC pins on the chip GND and
DGND are electrically isolated Both VCC pins and both ground pins
must be used
CLOCK PINS
CKI The Chip System Clock Input
CKO
The Chip System Clock Output (inversion of CKI)
Pins CKI and CKO are usually connected across an external
crystal
CK2
Clock Output (CKI divided by 2)
OTHER PINS
WO This is an active low open drain output that sig-
nals an illegal situation has been detected by the
Watch Dog logic
ST1 Bus Cycle Status Output indicates first opcode
fetch
ST2 Bus Cycle Status Output indicates machine
states (skip interrupt and first instruction cycle)
RESET is an active low input that forces the chip to re-
start and sets the ports in a TRI-STATE mode
RDY HLD has two uses selected by a software bit It’s ei-
ther a READY input to extend the bus cycle for
slower memories or a HOLD request input to put
the bus in a high impedance state for DMA pur-
poses
NC (no connection) do not connect anything to this
pin
EXM
External memory enable (active high) disables
internal ROM and maps it to external memory
EI External interrupt with vector address
FFF1 FFF0 (Rising falling edge or high low lev-
el sensitive) Alternately can be configured as
4th input capture
EXUI
External interrupt which is internally OR’ed with
the UART interrupt with vector address
FFF3 FFF2 (Active Low)
Connection Diagrams
Plastic and Ceramic Leaded Chip Carriers
Top View
TL DD 8801 – 11
See NS Package Number EL68A or V68A
See Part Selection for Ordering Information
12

12 Page





SeitenGesamt 36 Seiten
PDF Download[ HPC26003 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
HPC26003High-Performance microControllersNational Semiconductor
National Semiconductor
HPC26003(HPC16003 - HPC46003 / HPC16083 - HPC46083) High-Performance microControllersNational Semiconductor
National Semiconductor
HPC26004(HPC16064 - HPC46064 / HPC16004 - HPC46004) High-Performance microControllerNational Semiconductor
National Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche