PDF HS1-80C86RH Data sheet ( Hoja de datos )

Número de pieza	HS1-80C86RH
Descripción	Radiation Hardened 16-Bit CMOS Microprocessor
Fabricantes	Intersil Corporation
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No Preview Available ! HS-80C86RH September 1995 Radiation Hardened 16-Bit CMOS Microprocessor Features Description • Radiation Hardened - Latch Up Free EPl-CMOS - Total Dose >100K RAD (Si) - Transient Upset >108 RAD (Si)/s • Low Power Operation - ICCSB = 500µA (Max) - ICCOP = 12mA/MHz (Max) The Intersil HS-80C86RH high performance radiation hardened 16-bit CMOS CPU is manufactured using a hardened ﬁeld, self aligned silicon gate CMOS process. Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user conﬁguration to achieve the highest performance level. Industry standard operation allows use of existing NMOS 8086 hardware and software designs. • Pin Compatible with NMOS 8086 and Intersil 80C86 • Completely Static Design DC to 5MHz • 1MB Direct Memory Addressing Capability • 24 Operand Addressing Modes • Bit, Byte, Word, and Block Move Operations • 8-Bit and 16-Bit Signed/Unsigned Arithmetic - Binary or Decimal - Multiply and Divide • Bus-hold Circuitry Eliminates Pull-up Resistors for CMOS Designs • Hardened Field, Self-Aligned, Junction-Isolated CMOS Process • Single 5V Power Supply • Military Temperature Range -35oC to +125oC • Minimum LET for Single Event Upset -6MEV/mg/cm2 (Typ) Ordering Information PART NUMBER HS1-80C86RH-8 HS1-80C86RH-Q HS9-80C86RH-8 HS9-80C86RH-Q HS9-80C86RH-SAMPLE HS1-80C86RH-SAMPLE HS9-80C86RH-PROTO HS1-80C86RH-PROTO TEMPERATURE RANGE -35oC to +125oC -35oC to +125oC -35oC to +125oC -35oC to +125oC 25oC 25oC -35oC to +125oC -35oC to +125oC SCREENING LEVEL Intersil Class B Equivalent Intersil Class S Equivalent Intersil Class B Equivalent Intersil Class S Equivalent Sample Sample Prototype Prototype PACKAGE 40 Lead Braze Seal DIP 40 Lead Braze Seal DIP 42 Lead Braze Seal Flatpack 42 Lead Braze Seal Flatpack 42 Lead Braze Seal Flatpack 40 Lead Braze Seal DIP 42 Lead Braze Seal Flatpack 40 Lead Braze Seal DIP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 856 Spec Number 518055 File Number 3035.1 1 page HS-80C86RH Pin Description (Continued) SYMBOL PIN NUMBER TYPE DESCRIPTION RESET 21 I RESET: causes the processor to immediately terminate its present activity. The signal must change from LOW to HIGH and remain active HIGH for at least 4 CLK cycles. It restarts execution, as described in the Instruction Set description, when RESET returns LOW. RESET is internally synchronized. CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. VDD 40 VDD: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for decoupling. GND 1, 20 GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is recommended for decoupling. MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are discussed in the following sections. The following pin function descriptions are for the HS-80C86RH system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to maximum mode are described below. S0, S1, S2 26-28 O STATUS: is active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3 or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory and I/O access control signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These status lines are encoded. These signals are held at a high impedance logic one state during “grant sequence”. S2 S1 S0 0 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive RQ/GT0 RQ/GT1 31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 hav- ing higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence Timing.) 1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to the HS-80C86RH (pulse 1). 2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the HS-80C86RH to the requesting master (pulse 2) indicates that the HS-80C86RH has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPU’s bus interface unit is dis- connected logically from the local bus during “grant sequence”. 3. A pulse 1 CLK wide from the requesting master indicates to the HS-80C86RH (pulse 3) that the “hold” request is about to end and that the HS-80C86RH can reclaim the local bus at the next CLK. The CPU then enters T4 (or T1 if no bus cycles pending). Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one idle CLK cycle after each bus exchange. Pulses are active low. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met: 1. Request occurs on or before T2. 2. Current cycle is not the low byte of a word (on an odd address). 3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A locked instruction is not currently executing. If the local bus is idle when the request is made the two possible events will follow: 1. Local bus will be released during the next cycle. 2. A memory cycle will start within 3 CLKs. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. Spec Number 518055 860 5 Page Speciﬁcations HS-80C86RH TABLE 3A. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETERS SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS TIMING RESPONSES Address Hold Time Address Float Delay (Note 2) Data Valid Delay Data Hold Time Data Hold Time After WR Status Float Delay (Note 2) Address Float to Read Active (Note 2) TCLAX TCLAZ TCLDV TCLDX2 TWHDX TCHSZ TAZRL VDD = 4.75V and 5.25V Min and Max Mode VDD = 4.75V and 5.25V Min and Max Mode VDD = 4.75V and 5.25V Min and Max Mode VDD = 4.75V and 5.25V Min and Max Mode VDD = 4.75V and 5.25V Min Mode VDD = 4.75V and 5.25V Max Mode VDD = 4.75V and 5.25V Min and Max Mode -35oC < TA < +125oC 10 -35oC < TA < +125oC TCLAX -35oC < TA < +125oC 10 -35oC < TA < +125oC 10 -35oC < TA < +125oC TCLCL - 30 -35oC < TA < +125oC - -35oC < TA < +125oC 0 - 80 110 - - 80 - ns ns ns ns ns ns ns NOTES: 1. All measurements referenced to device ground. 2. Output drivers disabled. Bus hold circuitry still active. 3. The parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. TABLE 3B. ELECTRICAL PERFORMANCE CHARACTERISTICS Timing Signals at HS-82C85RH or 82C88 for Reference Only. PARAMETERS SYMBOL CONDITIONS TEMPERATURE RDY Setup Time into HS-82C85RH (Note 1) RDY Hold Time into HS-82C85RH (Note 1) Command Active Delay Command Inactive Status Valid to ALE High Status Valid to MCE High CLK Low to ALE Valid CLK Low to MCE High ALE Inactive Delay MCE Inactive Delay Control Active Delay Control Inactive Delay TR1VCL Min and Max Mode TCLR1X Min and Max Mode TCLML Max Mode Only TCLMH Max Mode Only TSVLH Max Mode Only TSVMCH Max Mode Only TCLLH Max Mode Only TCLMCH Max Mode Only TCHLL Max Mode Only TCLMCL Max Mode Only TCVNV Max Mode Only TCVNX Max Mode Only -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC -35oC < TA < +125oC NOTE: 1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. LIMITS MIN MAX UNITS 35 - ns 0- ns 5 35 ns 5 35 ns - 20 ns - 30 ns - 20 ns - 25 ns 4 18 ns - 15 ns 5 45 ns 10 45 ns TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: See 25oC limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7 and 9). Spec Number 518055 866 11 Page

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