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PDF HS-3282 Data sheet ( Hoja de datos )
| Número de pieza | HS-3282 | |
| Descripción | CMOS ARINC Bus Interface Circuit | |
| Fabricantes | Intersil Corporation | |
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HS-3282
REFERENCE AN400
March 1997
CMOS ARINC Bus Interface Circuit
Features
• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Receivers, Connecting Directly
to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
TEMP. RANGE
-55oC to +125oC
PART NUMBER
HS1-3282-8
PKG.
NO.
F40.6
-40oC to +85oC
-55oC to +125oC
5962-8688001QA
HS4-3282-9+
HS4-3282-8
F40.6
J44.A
J44.A
5962-8688001XA J44.A
Description
The HS-3282 is a high performance CMOS bus interface
circuit that is intended to meet the requirements of ARINC
Specification 429, and similar encoded, time multiplexed
serial data protocols. This device is intended to be used with
the HS-3182, a monolithic Dl bipolar differential line driver
designed to meet the specifications of ARINC 429. The
ARINC 429 bus interface circuit consists of two (2) receivers
and a transmitter operating independently as shown in
Figure 1. The two receivers operate at a frequency that is ten
(10) times the receiver data rate, which can be the same or
different from the transmitter data rate. Although the two
receivers operate at the same frequency, they are
functionally independent and each receives serial data asyn-
chronously. The transmitter section of the ARINC bus
interface circuit consists mainly of a First-In First-Out (FIFO)
memory and timing circuit. The FIFO memory is used to hold
up to eight (8) ARINC data words for transmission serially.
The timing circuit is used to correctly separate each ARINC
word as required by ARINC Specification 429. Even though
ARINC Specification 429 specifies a 32-bit word, including
parity, the HS-3282 can be programmed to also operate with
a word length of 25 bits. The incoming receiver data word
parity is checked, and a parity status is stored in the receiver
latch and output on Pin BD08 during the 1st word. [A logic
“0” indicates that an odd number of logic “1” s were received
and stored; a logic “1” indicates that an even number of logic
“1”s were received and stored]. In the transmitter the parity
generator will generate either odd or even parity depending
upon the status of PARCK control signal. A logic “0” on BD12
will cause odd parity to be used in the output data stream.
Versatility is provided in both the transmitter and receiver by
the external clock input which allows the bus interface circuit
to operate at data rates from 0 to 100 kilobits. The external
clock must be ten (10) times the data rate to insure no data
ambiguity.
The ARINC bus interface circuit is fully guaranteed to
support the data rates of ARINC specification 429 over both
the voltage (±5%) and full military temperature range. It
interfaces with UL, CMOS or NMOS support circuitry, and
uses the standard 5-volt VCC supply.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-183
File Number 2964.2
1 page  
HS-3282
Operational Description
The HS-3282 is designed to support ARINC Specification
429 and other serial data protocols that use a similar format
by collecting the receiving, transmitting, synchronizing,
timing and parity functions on a single, low power LSl circuit.
It goes beyond the ARlNC requirements by providing for
either odd or even parity, and giving the user a choice of
either 25 or 32-bit word lengths. The receiver and transmitter
sections operate independently of each other. The serial-to-
parallel conversion required of the receiver and the parallel-
to-serial conversion requirements of the transmitter have
been incorporated into the bus interface circuit.
Provisions have been made through the external clock input
to provide data rate flexibility. This requires an external clock
that is 10 times the data rate.
To obtain the flexibility discussed above, a number of
external control signals are required, To reduce the pin count
requirements, an internal control word register is used. The
control word is latched from the data bus into the register by
the Control Word Strobe (CWSTR) signal going to a logic
“1”. Eleven (11) control functions are used, and along with
the Bus Data (BD) line are listed below:
Control Word
PIN NAME
BD05
BD06
BD07
BD08
BD09
BD10
BD11
BD12
BD13
BD14
BD15
SYMBOL
SLFTST
SDENB1
X1
Y1
SDENB2
X2
Y2
PARCK
TXSEL
RCVSEL
WLSEL
FUNCTION
Connects the self test signal from the transmitter directly to the receiver shift registers, bypassing the input
receivers. Receiver 1 receives Data True and Receiver 2 receives Data Not. Note that the transmitter output
remains active. (Logic “0” on SLFTST Enables Self Test).
Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder).
If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be
accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
If SDENBI = “1” then this bit is compared with ARINC Data Bit #10. If X1 also matches (see X1), the word will
be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.
Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder).
If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be
accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will
be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.
Signal used to invert the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity. Logic
“I” selects even parity.
Selects high or low Transmitter data rate. If TXSEL = “0” then transmitter data rate is equal to the clock rate
divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80).
Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock
rate divided by ten (10), if RCVSEL = “1 “then the received data rate should be equal to the clock rate divided
by eighty (80).
Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format
will be selected.
ARlNC 429 DATA FORMAT as input to the Receiver and out-
put from the Transmitter is as follows:
TABLE 1. ARINC 429 32-BIT DATA FORMAT
ARINC BIT #
1-8
9 - 10
11
12 - 27
28
29
30, 31
32
FUNCTION
Label
SDl or Data
LSB
Data
MSB
Sign
SSM
Parity Status
This format is shuffled when seen on the sixteen bidirec-
tional input/outputs. The format shown below is used from
the receivers and input to the transmitter:
TABLE 2A. WORD 1 FORMAT
BI-DIRECTIONAL
BIT #
15, 14
13
12, 11
10, 9
8
7 - 00
FUNCTION
Data
LSB
SDl or Data
SSM Status
Parity Status
Label
ARINC BlT #
13, 12
11
10, 9
31, 30
32
1-8
5-187
5 Page 
HS-3282
AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8) (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Data Word Gap Time 1/
Data Word Gap Time 2/
Data Transmission Word to TX/R Set Time
Enable Transmit Turnoff Time
REPEATER OPERATION TIMING
TGAP
TGAP
TDTX/R
TENTX/R
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
39.6
316.8
-
0
40.4
323.2
400
-
Data Enable to Parallel Load Delay Time
Data Enable Hold for Parallel Load Time
Enable Transmit Delay Time
NOTES:
1. 100kHz Data Rate.
2. 12.5kHz Data Rate.
TENPL
TPLEN
TTX/REN
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
0-
0-
0-
UNITS
µs
µs
ns
ns
ns
ns
ns
Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
LIMITS
MIN MAX
UNITS
Differential Input Capacitance
Input Capacitance to VDD
lnput Capacitance to GND
Input Capacitance
Output Capacitance
Clock Rise Time
CD
CH
CG
Cl
CO
TLHC
VDD = Open, f = 1MHz, Note 2, 3
VDD = GND, f = 1MHz, Note 2, 3
VDD = Open, f = 1MHz, Note 2, 3
VDD = Open, f = 1MHz, Note 2, 4
VDD = Open, f = 1MHz, Note 2, 5
CLK = 1MHz, From 0.7V to 3.5V
- 20 pF
- 20 pF
- 20 pF
- 15 pF
- 15 pF
- 10 ns
Clock Fall Time
THLC
CLK = 1MHz, From 3.5V to 0.7V
- 10 ns
Input Rise Time
TLHI
From 0.7V to 3.5V, Note 6
- 15 ns
Input Fall Time
THLI
From 3.5V to 0.7V, Note 6
- 15 ns
NOTES:
1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes affecting these parameters.
2. All measurements are referenced to device GND.
3. Pins 2-3, 4-5.
4. Pins 8-10, 28, 29, 33, 34, 37, 39.
5. Pins 6, 7, 11-20, 22-27, 30-32, 38.
6. Pins 8-20, 22-29, 33, 34.
5-193
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