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Teilenummer | HUF75542S3S |
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Beschreibung | 75A/ 80V/ 0.014 Ohm/ N-Channel/ UltraFET Power MOSFETs | |
Hersteller | Intersil Corporation | |
Logo | ||
Gesamt 11 Seiten TM
Data Sheet
HUF75542P3, HUF75542S3S
June 2000 File Number 4845.2
75A, 80V, 0.014 Ohm, N-Channel,
UltraFET Power MOSFETs
Packaging
JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
HUF75542P3
Symbol
GATE
SOURCE
DRAIN
(FLANGE)
HUF75542S3S
D
G
S
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.014Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Electrical Models
- Spice and SABER© Thermal Impedance Models
- www.intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75542P3
TO-220AB
75542P
HUF75542S3S
TO-263AB
75542S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF75542S3ST.
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
HUF75542P3, HUF75542S3S UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
80
80
±20
75
58
Figure 4
Figures 6, 14, 15
V
V
V
A
A
Power Dissipation . . .
Derate Above 25oC
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PD
...
230
1.54
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTE:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
SABER© is a Copyright of Analogy Inc.
HUF75542P3, HUF75542S3S
Test Circuits and Waveforms (Continued)
VGS
Ig(REF)
VDS
RL
DUT
+
VDD
-
FIGURE 16. GATE CHARGE TEST CIRCUIT
VDD
VDS
Qg(TOT)
VGS
VGS = 2V
0 Qg(TH)
Qgs
Ig(REF)
0
Qg(10)
Qgd
VGS = 10V
VGS = 20V
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
RL
VGS
RGS
DUT
+
VDD
-
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 19. SWITCHING TIME WAVEFORM
6
6 Page | ||
Seiten | Gesamt 11 Seiten | |
PDF Download | [ HUF75542S3S Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
HUF75542S3S | 75A/ 80V/ 0.014 Ohm/ N-Channel/ UltraFET Power MOSFETs | Fairchild Semiconductor |
HUF75542S3S | 75A/ 80V/ 0.014 Ohm/ N-Channel/ UltraFET Power MOSFETs | Intersil Corporation |
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