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Teilenummer | HUF75339P3 |
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Beschreibung | 75A/ 55V/ 0.012 Ohm/ N-Channel UltraFET Power MOSFETs | |
Hersteller | Intersil Corporation | |
Logo | ||
Gesamt 9 Seiten HUF75339G3, HUF75339P3, HUF75339S3S
Data Sheet
June 1999 File Number 4363.5
75A, 55V, 0.012 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET™ process.
This advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75339.
Ordering Information
PART NUMBER
PACKAGE
BRAND
HUF75339G3
TO-247
75339G
HUF75339P3
TO-220AB
75339P
HUF75339S3S
TO-263AB
75339S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75339S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
Features
• 75A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER©
Models
- SPICE and SABER Thermal Impedance Models
Available on the WEB at:
www.Intersil.com/families/models.htm
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-220AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(TAB)
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
121
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
SABER© is a Copyright of Analogy, Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HUF75339G3, HUF75339P3, HUF75339S3S
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VGS
IG(REF)
VDS
RL
DUT
+
VDD
-
FIGURE 16. GATE CHARGE TEST CIRCUIT
VDD
VDS
Qg(TOT)
VGS
VGS = 2V
0 Qg(TH)
Qgs
Ig(REF)
0
Qg(10)
Qgd
VGS = 10V
VGS = 20V
FIGURE 17. GATE CHARGE WAVEFORM
VDS
RL
VGS
VGS
RGS
DUT
+
VDD
-
FIGURE 18. SWITCHING TIME TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
126
6 Page | ||
Seiten | Gesamt 9 Seiten | |
PDF Download | [ HUF75339P3 Schematic.PDF ] |
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