PDF HSP45256JI-33 Data sheet ( Hoja de datos )

Número de pieza	HSP45256JI-33
Descripción	Binary Correlator
Fabricantes	Intersil Corporation
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No Preview Available ! Data Sheet HSP45256 May 1999 File Number 2814.4 Binary Correlator The Intersil HSP45256 is a high-speed, 256 tap binary correlator. It can be conﬁgured to perform one-dimensional or two-dimensional correlations of selectable data precision and length. Multiple HSP45256’s can be cascaded for increased correlation length. Unused taps can be masked out for reduced correlation length. The correlation array consists of eight 32-tap stages. These may be cascaded internally to compare 1, 2, 4 or 8-bit input data with a 1-bit reference. Depending on the number of bits in the input data, the length of the correlation can be up to 256, 128, 64, or 32 taps. The HSP45256 can also be conﬁgured as two separate correlators with window sizes from 4 by 32 to 1 by 128 each. The mask register can be used to prevent any subset of the 256 bits from contributing to the correlation score. The output of the correlation array (correlation score) feeds the weight and sum logic, which gives added ﬂexibility to the data format. In addition, an offset register is provided so that a preprogrammed value can be added to the correlation score. This result is then passed through a user programmable delay stage to the cascade summer. The delay stage simpliﬁes the cascading of multiple correlators by compensating for the latency of previous correlators. The Binary Correlator is conﬁgured by writing a set of control registers via a standard microprocessor interface. To simplify operation, both the control and reference registers are double buffered. This allows the user to load new mask and reference data while the current correlation is in progress. Features • Reconﬁgurable 256 Stage Binary Correlator • 1-Bit Reference x 1, 2, 4, or 8-Bit Data • Separate Control and Reference Interfaces • 25.6, 33MHz Versions • Conﬁgurable for 1-D and 2-D Operation • Double Buffered Mask and Reference • Programmable Output Delay • Cascadable • Standard Microprocessor Interface Applications • Radar/Sonar • Spread Spectrum Communications • Pattern/Character Recognition - Error Correction Coding Ordering Information PART NUMBER HSP45256JC-25 HSP45256JC-33 HSP45256GC-25 HSP45256GC-33 HSP45256JI-25 HSP45256JI-33 TEMP. RANGE (oC) PACKAGE 0 to 70 84 Ld PLCC 0 to 70 84 Ld PLCC 0 to 70 85 Ld PGA 0 to 70 85 Ld PGA -40 to 85 84 Ld PLCC -40 to 85 84 Ld PLCC PKG. NO. N84.1.15 N84.1.15 G85.A G85.A N84.1.15 N84.1.15 Block Diagram DIN0-7 DREF0-7 DOUT 256 TAP CORRELATION ARRAY DREFOUT CSCORE WEIGHT AND SUM MUX DOUT0-7 AUXOUT0-8 DCONT0-7 A0-2 CASIN0-12 CONTROL DELAY CASCADE SUMMER CASOUT0-12 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 1 page HSP45256 Block Diagram A(2:0) CLOAD DECODE DCONT(7:0) RLOAD TXFR CONFIG OFFAL OFFAM DELAY OFFBL OFFBM MASK DIN7 DREF7 R E >G R E >G TC (001) R E >G R6 E >G (000) R8 E >G DO7 32 TAP CORRELATOR STAGE RO7 MR7 + R E >G 5 TC CONFIG(4:0) DATA OUT RO7 CORRELATION SCORE OUT CO7 DO7 DIN6 R E >G CONFIG(4:0) RO7 DREF6 R E >G DO6 32 TAP CORRELATOR STAGE RO6 MR6 + R E >G DATA OUT RO6 CO6 DO1 DIN0 R E >G DREF0 R E >G CONFIG(4:0) RO1 32 TAP CORRELATOR STAGE MR0 DO0 RO0 + R E >G CLK CASIN(12:0) OEA OEC NOTE: All registers clocked with CLK unless otherwise speciﬁed. CORRELATOR BLOCK DIAGRAM MUX ARRAY 5 RO0 CO0 REFERENCE OUT CASIN(12:0) OEA OEC DOUT(7:0) 5 Page HSP45256 BIT POSITION FUNCTION 7-1 Reserved 0 Offset Register B MSB TABLE 7. MS OFFSET REGISTER B DESTINATION ADDRESS = 5 (101) DESCRIPTION Reserved. Program to zero. OFFB8: Most significant bit of Offset Register B. In dual correlator mode, this register is used for the correlator whose output appears on the AUXOUT pins. BIT POSITION FUNCTION 7-0 Offset Register B LSB TABLE 8. LS OFFSET REGISTER B DESTINATION ADDRESS = 6 (110) DESCRIPTION OFFB0-7: Least significant bits of Offset Register B. 11 11 Page

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