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PDF PIC16C717 Data sheet ( Hoja de datos )

Número de pieza PIC16C717
Descripción 18/20-Pin/ 8-Bit CMOS Microcontrollers
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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PIC16C717/770/771
18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
Device
Memory
Program Data
Pins
A/D A/D
Resolution Channels
x14 x8
PIC16C717 2K 256 18, 20 10 bits
6
PIC16C770 2K 256 20
12 bits
6
PIC16C771 4K 256 20
12 bits
6
• Interrupt capability (up to 10 internal/external
interrupt sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Selectable oscillator options:
- INTRC - Internal RC, dual speed (4 MHz and
37 kHz nominal) dynamically switchable for
power savings
- ER - External resistor, dual speed (user
selectable frequency and 37 kHz nominal)
dynamically switchable for power savings
- EC - External clock
- HS - High speed crystal/resonator
- XT - Crystal/resonator
- LP - Low power crystal
• Low power, high speed CMOS EPROM
technology
• In-Circuit Serial Programming™(ICSP™
• Wide operating voltage range: 2.5V to 5.5V
• 15 I/O pins with individual control for:
- Direction (15 pins)
- Digital/Analog input (6 pins)
- PORTB interrupt on change (8 pins)
- PORTB weak pull-up (8 pins)
- High voltage open drain (1 pin)
• Commercial and Industrial temperature ranges
• Low power consumption:
- < 2 mA @ 4V, 4 MHz
- 11 A typical @ 2.5V, 37 kHz
- < 1 A typical standby current
Pin Diagram
20-Pin PDIP, SOIC, SSOP
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
RA5/MCLR/VPP
VSS
AVSS
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RB0/AN4/INT
RB1/AN5/SS
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
AVDD
RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Enhanced Capture, Compare, PWM (ECCP)
module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
- Enhanced PWM:
- Single, Half-Bridge and Full-Bridge Output
modes
- Digitally programmable deadband delay
• Analog-to-Digital converter:
- PIC16C770/771 12-bit resolution
- PIC16C717 10-bit resolution
• On-chip absolute bandgap voltage reference
generator
• Programmable Brown-out Reset (PBOR)
circuitry
• Programmable Low-Voltage Detection (PLVD)
circuitry
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
- I2C™ compatible including Master mode
support
• Program Memory Read (PMR) capability for look-
up table, character string storage and checksum
calculation purposes
1999-2013 Microchip Technology Inc.
DS41120C-page 1

1 page




PIC16C717 pdf
PIC16C717/770/771
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicroTM
Mid-Range MCU Family Reference Manual,
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip website. The Reference Manual should
be considered a complementary document to this data
sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
There are three devices (PIC16C717, PIC16C770 and
PIC16C771) covered by this data sheet. The
PIC16C717 device comes in 18/20-pin packages and
the PIC16C770/771 devices come in 20-pin packages.
The following two figures are device block diagrams of
the PIC16C717 and the PIC16C770/771.
FIGURE 1-1:
PIC16C717 BLOCK DIAGRAM
EPROM
Program
Memory
2K x 14
Program
Bus
14
13
Program Counter
8 Level Stack
(13-bit)
Program Memory
Read (PMR)
Instruction reg
Direct Addr 7
Internal
4 MHz, 37 kHz
and ER mode
Instruction
Decode &
Control
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
VDD, VSS
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Data Bus
8
RAM
File
Registers
256 x 8
RAM
9 Addr(1)
Addr MUX
Indirect
8 Addr
FSR reg
STATUS reg
3 MUX
ALU
8
W reg
PORTA
PORTB
RA0/AN0
RA1/AN1/LVDIN
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/AN4/INT
RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1D
10-bit
ADC
Bandgap
Reference
Low-voltage
Detect
Timer0
Timer1
Timer2
Enhanced CCP
(ECCP)
Master
Synchronous
Serial Port (MSSP)
Note 1: Higher order bits are from the STATUS register.
1999-2013 Microchip Technology Inc.
DS41120C-page 5

5 Page





PIC16C717 arduino
PIC16C717/770/771
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Details
POR,
on
BOR
Page:
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 23
01h TMR0
Timer0 module’s register
xxxx xxxx 45
02h(3)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 22
03h(3)
STATUS
IRP RP1 RP0
TO
PD
Z
DC
C 0001 1xxx 14
04h(3)
FSR
Indirect data memory address pointer
xxxx xxxx 23
05h PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0 xxxx 0000 25
06h PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xx11 33
07h — Unimplemented
——
08h — Unimplemented
——
09h
0Ah(1,3)
0B h(3)
PCLATH
INTCON
Unimplemented
——
GIE PEIE
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
---0 0000
0000 000x
22
16
0Ch PIR1
— ADIF —
— SSPIF CCP1IF TMR2IF TMR1IF -0---0000 18
0Dh PIR2
LVDIF
BCLIF
0--- 0--- 20
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx 47
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx 47
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 47
11h TMR2
Timer2 module’s register
0000 0000 51
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 51
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 70
14h SSPCON WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 67
15h CCPR1L Capture/Compare/PWM Register1 (LSB)
xxxx xxxx 54
16h CCPR1H Capture/Compare/PWM Register1 (MSB)
xxxx xxxx 54
17h
CCP1CON PWM1M1 PWM1M0 DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 53
18h — Unimplemented
——
19h — Unimplemented
——
1Ah — Unimplemented
——
1Bh — Unimplemented
——
1Ch — Unimplemented
——
1Dh — Unimplemented
——
1Eh ADRESH A/D High Byte Result Register
xxxx xxxx 107
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0 GO/DONE CHS3
ADON 0000 0000 107
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
These registers can be addressed from any bank.
1999-2013 Microchip Technology Inc.
DS41120C-page 11

11 Page







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