PDF ADF7020 Data sheet ( Hoja de datos )

Número de pieza	ADF7020
Descripción	High Performance ISM Band FSK/ASK Transceiver IC
Fabricantes	Analog Devices
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Data Sheet High Performance, ISM Band, FSK/ASK Transceiver IC ADF7020 FEATURES Low power, low IF transceiver Frequency bands 431 MHz to 478 MHz 862 MHz to 956 MHz Data rates supported 0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2.3 V to 3.6 V power supply Programmable output power −16 dBm to +13 dBm in 0.3 dBm steps Receiver sensitivity −119 dBm at 1 kbps, FSK −112 dBm at 9.6 kbps, FSK −106.5 dBm at 9.6 kbps, ASK Low power consumption 19 mA in receive mode 26.8 mA in transmit mode (10 dBm output) −3 dBm IIP3 in high linearity mode On-chip VCO and fractional-N PLL On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) compensates for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at 431 MHz to 478 MHz Digital RSSI Integrated Tx/Rx switch Leakage current of <1 μA in power-down mode APPLICATIONS Low cost wireless data transfer Remote control/security systems Wireless metering Keyless entry Home automation Process and building control Wireless voice RSET CREG[1:4] FUNCTIONAL BLOCK DIAGRAM ADCIN MUXOUT RLNA LDO(1:4) OFFSET CORRECTION TEMP SENSOR TEST MUX ADF7020 RFIN RFINB RFOUT LNA GAIN IF FILTER RSSI MUX 7-BIT ADC FSK/ASK DEMODULATOR OFFSET CORRECTION AGC CONTROL FSK MOD CONTROL GAUSSIAN FILTER Σ-∆ MODULATOR AFC CONTROL DIVIDERS/ MUXING DIV P N/N + 1 VCO CP PFD DIV R OSC CLK DIV DATA SYNCHRONIZER Tx/Rx CONTROL SERIAL PORT VCOIN CPOUT OSC1 OSC2 Figure 1. CLKOUT CE DATA CLK DATA I/O INT/LOCK SLE SDATA SREAD SCLK Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ADF7020 SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All measurements are performed using the EVAL-ADF7020DBZ1 through EVAL-ADF7020DBZ3 using the PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate FSK/GFSK OOK/ASK OOK/ASK Frequency Shift Keying GFSK/FSK Frequency Deviation2, 3 Deviation Frequency Resolution Gaussian Filter BT Amplitude Shift Keying ASK Modulation Depth PA Off Feedthrough in OOK Mode Transmit Power4 Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Flatness Programmable Step Size −20 dBm to +13 dBm Integer Boundary Reference Harmonics Second Harmonic Third Harmonic All Other Harmonics VCO Frequency Pulling, OOK Mode Optimum PA Load Impedance5 RECEIVER PARAMETERS FSK/GFSK Input Sensitivity Min 862 902 928 431 440 RF/256 0.15 0.15 0.3 1 4.88 100 −20 Typ 0.5 −50 ±1 ±1 ±1 0.3125 −55 −65 −27 −21 −35 30 39 + j61 48 + j54 54 + j94 Sensitivity at 1 kbps Sensitivity at 9.6 kbps Sensitivity at 200 kbps OOK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps −119.2 −112.8 −100 −116 −106.5 Max Unit 870 MHz 928 MHz 956 MHz 440 MHz 478 MHz 24 MHz 200 kbps 641 kbps 100 kbaud 110 kHz 620 kHz Hz 30 dB dBm +13 dBm dB dB dB dB dBc dBc dBc dBc dBc kHz rms Ω Ω Ω dBm dBm dBm dBm dBm Test Conditions VCO adjust = 0, VCO bias = 10 VCO adjust = 3, VCO bias = 10 VCO adjust = 3, VCO bias = 12, VDD = 2.7 V to 3.6 V VCO adjust = 0, VCO bias = 10 VCO adjust = 3, VCO bias = 12 Using Manchester encoding PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz VDD = 3.0 V, TA = 25°C From −40°C to +85°C From 2.3 V to 3.6 V at 915 MHz, TA = 25°C From 902 MHz to 928 MHz, 3 V, TA = 25°C 50 kHz loop BW Unfiltered conductive DR = 9.6 kbps FRF = 915 MHz FRF = 868 MHz FRF = 433 MHz At BER = 1E − 3, FRF = 915 MHz, LNA and PA matched separately6 FDEV = 5 kHz, high sensitivity mode7 FDEV = 10 kHz, high sensitivity mode FDEV = 50 kHz, high sensitivity mode At BER = 1E − 3, FRF = 915 MHz High sensitivity mode High sensitivity mode Rev. E \| Page 5 of 47 5 Page Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADF7020 VCOIN 1 CREG1 2 VDD1 3 RFOUT 4 RFGND 5 RFIN 6 RFINB 7 RLNA 8 VDD4 9 RSET 10 CREG4 11 GND4 12 ADF7020 TOP VIEW (Not to Scale) 36 CLKOUT 35 DATA CLK 34 DATA I/O 33 INT/LOCK 32 VDD2 31 CREG2 30 ADCIN 29 GND2 28 SCLK 27 SREAD 26 SDATA 25 SLE NOTES 1. EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. 2 CREG1 Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 3 VDD1 Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together. 4 RFOUT The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. 5 RFGND Ground for Output Stage of Transmitter. All GND pins should be tied together. 6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. 7 RFINB Complementary LNA Input. See the LNA/PA Matching section. 8 RLNA 9 VDD4 External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. 10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance. 11 CREG4 Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. 12 GND4 Ground for LNA/MIXER Block. 13 to 18 MIX_I, MIX_I, MIX_Q, MIX_Q, FILT_I, FILT_I Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 19, 22 GND4 Ground for LNA/MIXER Block. 20, 21, 23 FILT_Q, FILT_Q, TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. 24 CE Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. 25 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the fourteen latches. A latch is selected using the control bits. 26 SDATA Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input. Rev. E \| Page 11 of 47 11 Page

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