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ADF4360-3 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4360-3
Beschreibung Integrated Synthesizer and VCO
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
ADF4360-3 Datasheet, Funktion
Data Sheet
Integrated Synthesizer and VCO
ADF4360-3
FEATURES
GENERAL DESCRIPTION
Output frequency range: 1600 MHz to 1950 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4360-3 is a fully integrated integer-N synthesizer
and voltage controlled oscillator (VCO). The ADF4360-3 is
designed for a center frequency of 1750 MHz. In addition, there
is a divide-by-2 option available, whereby the user gets an RF
output of between 800 MHz and 975 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
CE RSET
REFIN
CLK
DATA
LE
ADF4360-3
14-BIT R
COUNTER
24-BIT
DATA REGISTER
24-BIT
FUNCTION
LATCH
LOCK
DETECT
MULTIPLEXER
MUTE
CHARGE
PUMP
PHASE
COMPARATOR
MUXOUT
CP
VVCO
VTUNE
CC
CN
INTEGER
REGISTER
PRESCALER
P/P+1
N = (BP + A)
13-BIT B
COUNTER
LOAD
LOAD
5-BIT A
COUNTER
VCO
CORE
DIVSEL = 1
OUTPUT
STAGE
RFOUTA
RFOUTB
÷2
AGND
DIVSEL = 2
DGND
CPGND
Figure 1.
Rev. E
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ADF4360-3 Datasheet, Funktion
Data Sheet
ADF4360-3
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
1See the Power-Up section for the recommended power-up procedure for this device.
Test Conditions/Comments
LE Setup Time
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
CLOCK
DATA
DB23 (MSB)
t2 t3
DB22
t4 t5
DB2
DB1 (LSB)
(CONTROL BIT C2)
LE
t1
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. E | Page 5 of 24

6 Page









ADF4360-3 pdf, datenblatt
Data Sheet
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RFOUTA and RFOUTB pins of the ADF4360-3 are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 15. To allow the user to
optimize the power dissipation vs. the output power require-
ments, the tail current of the differential pair is programmable
via Bits PL1 and PL2 in the control latch. Four current levels
may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give
output power levels of −12 dBm, −9 dBm, −6 dBm, and −3dBm,
respectively, using a 50 Ω resistor to VDD and ac coupling into a
50 Ω load. Alternatively, both outputs can be combined in a 1 +
1:1 transformer or a 180° microstrip coupler (see the Output
Matching section).
ADF4360-3
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360-3 is that the supply current
to the RF output stage is shut down until the device achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
RFOUTA
RFOUTB
VCO
BUFFER/
DIVIDE BY 2
Figure 15. Output Stage ADF4360-3
Rev. E | Page 11 of 24

12 Page





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