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PDF ADF4106 Data sheet ( Hoja de datos )
| Número de pieza | ADF4106 | |
| Descripción | PLL Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
PLL Frequency Synthesizer
ADF4106
FEATURES
GENERAL DESCRIPTION
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
Broadband wireless access
Satellite systems
Instrumentation
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.
Wireless LANS
Base stations for wireless radios
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
24-BIT INPUT
REGISTER 22
FUNCTION
LATCH
SDOUT
FROM
FUNCTION
LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
6-BIT
A COUNTER
CE AGND DGND
6
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
HIGH Z
19 AVDD
MUX
MUXOUT
SDOUT
M3 M2 M1
ADF4106
Figure 1.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4106
Data Sheet
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH)11
Normalized 1/f Noise (PN1_f)12
Phase Noise Performance13
900 MHz14
5800 MHz15
5800 MHz16
Spurious Signals
900 MHz14
5800 MHz15
5800 MHz16
B Version1 B Chips2 (typ) Unit
–223
−122
–223
−122
dBc/Hz typ
dBc/Hz typ
–92.5
−76.5
−83.5
−92.5
−76.5
−83.5
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
–90/–92
–65/–70
–70/–75
–90/–92
–65/–70
–70/–75
dBc typ
dBc typ
dBc typ
Test Conditions/Comments
PLL loop B/W = 500 kHz, measured at 100 kHz
offset
10 kHz offset; normalized to 1 GHz
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 1 MHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 1 MHz/2 MHz and 1 MHz PFD frequency
1 Operating temperature range (B Version) is –40°C to +85°C.
2 The B chip specifications are given as typical values.
3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4 AVDD = DVDD = 3 V.
5 AC coupling ensures AVDD/2 bias.
6 Guaranteed by design. Sample tested to ensure compliance.
7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.
8 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.
9 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.
10 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.
11 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
12 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
13 The phase noise is measured with the EV-ADF4106SD1Z evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
14 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
15 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz.
16 fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz.
TIMING CHARACTERISITICS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN,
unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit1 (B Version)
10
10
25
25
10
20
1 Operating temperature range (B Version) is –40°C to +85°C.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
Rev. F | Page 4 of 24
5 Page 
ADF4106
GENERAL DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REFIN pin on power-down.
POWER-DOWN
CONTROL
REFIN
NC 100k
SW2
NC
SW1
BUFFER
TO R COUNTER
NO SW3
Figure 17. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
BIAS
GENERATOR
1.6V
500
500
AVDD
RFINA
RFINB
Figure 18. RF Input Stage
AGND
PRESCALER (P/P +1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A counter and
B counter. The prescaler is programmable. It can be set in soft-
ware to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value, and is given by (P2 − P).
Data Sheet
A COUNTER AND B COUNTER
The A counter and B CMOS counter combine with the dual
modulus prescaler to allow a wide ranging division ratio in the
PLL feedback counter. The counters are specified to work when
the prescaler output is 325 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is
fVCO
P
B
A
f REFIN
R
where:
fVCO is the output frequency of the external voltage controlled
oscillator (VCO).
P is the preset modulus of the dual-modulus prescaler
(8/9, 16/17, etc.).
B is the preset divide ratio of the binary 13-bit counter
(3 to 8191).
A is the preset divide ratio of the binary 6-bit swallow
counter (0 to 63).
fREFIN is the external reference frequency oscillator.
N = BP + A
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
MODULUS
CONTROL
13-BIT B
COUNTER
LOAD
LOAD
6-BIT A
COUNTER
TO PFD
N DIVIDER
Figure 19. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
Rev. F | Page 10 of 24
11 Page | ||
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| PDF Descargar | [ Datasheet ADF4106.PDF ] | |
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