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PDF ADE7755 Data sheet ( Hoja de datos )
| Número de pieza | ADE7755 | |
| Descripción | Energy Metering IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Energy Metering IC with Pulse Output
ADE7755
FEATURES
High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs, F1 and F2
High frequency output CF is intended for calibration and
supplies instantaneous active power
Synchronous CF and F1/F2 outputs
Logic output REVP provides information regarding the sign
of the active power
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Programmable gain amplifier (PGA) in the current channel
facilitates usage of small shunts and burden resistors
Proprietary ADCs and DSPs provide high accuracy over large
variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.5 V ± 8% (30 ppm/°C typical) with
external overdrive capability
Single 5 V supply, low power (15 mW typical)
Low cost CMOS process
GENERAL DESCRIPTION
The ADE7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements as
quoted in the IEC 1036 standard.
The only analog circuitry used in the ADE7755 is in the ADCs
and reference circuit. All other signal processing (for example,
multiplication and filtering) is carried out in the digital domain.
This approach provides superior stability and accuracy over
extremes in environmental conditions and over time.
The ADE7755 supplies average active power information on the
low frequency outputs, F1 and F2. These logic outputs can be
used to directly drive an electromechanical counter or interface to
an MCU. The CF logic output gives instantaneous active power
information. This output is intended to be used for calibration
purposes or for interfacing to an MCU.
The ADE7755 includes a power supply monitoring circuit on the
AVDD supply pin. The ADE7755 remains in a reset condition until
the supply voltage on AVDD reaches 4 V. If the supply falls below
4 V, the ADE7755 resets and no pulse is issued on F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Channel 1
is on or off. An internal no load threshold ensures that the
ADE7755 does not exhibit any creep when there is no load.
The ADE7755 is available in a 24-lead SSOP package.
V1P 5
V1N 6
V2P 8
V2N 7
FUNCTIONAL BLOCK DIAGRAM
G0 G1
16 15
AVDD
3
AGND
11
AC/DC
ADE7755
2
DVDD
1
DGND
21
POWER
SUPPLY MONITOR
PHASE
CORRECTION
...110101...
ADC
PGA
×1, ×2, ×8, ×16
HPF
MULTIPLIER
SIGNAL
PROCESSING
BLOCK
LPF
...11011001...
ADC
2.5V
4kΩ
REFERENCE
DIGITAL-TO-FREQUENCY
CONVERTER
9 RESET
10 17 18 12 14 13 20 22 24 23
REFIN/OUT CLKIN CLKOUT SCF S0 S1 REVP CF F1 F2
Figure 1.
1U.S. Patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
DVDD to DGND
DVDD to AVDD
Analog Input Voltage to AGND
V1P, V1N, V2P, and V2N
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
24-Lead SSOP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−6 V to +6 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
450 mW
112°C/W
215°C
220°C
ADE7755
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 20
5 Page 
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7755 is defined by the following formula:
PercentageError =
Energy Registered by the ADE7755 − True Energy ×100%
True Energy
Phase Error Between Channels
The high-pass filter (HPF) in Channel 1 has a phase lead response.
To offset this phase response and equalize the phase response
between channels, a phase compensation network is also placed
in Channel 1. The phase compensation network matches the
phase to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°
over a range of 40 Hz to 1 kHz. See Figure 30 and Figure 31.
Power Supply Rejection (PSR)
The PSR quantifies the ADE7755 measurement error as a
percentage of the reading when the power supplies are varied.
For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of the reading (see the Measurement Error definition).
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.
ADE7755
ADC Offset Error
The ADC offset error refers to the dc offset associated with the
analog inputs to the ADCs. It means that with the analog inputs
connected to AGND, the ADCs still see a small dc signal
(offset). The offset decreases with increasing gain in Channel 1.
This specification is measured at a gain of 1. At a gain of 16, the
dc offset is typically less than 1 mV. However, when the HPF is
switched on, the offset is removed from the current channel,
and the power calculation is not affected by this offset.
Gain Error
The gain error of the ADE7755 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in Channel 1.
The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the ADE7755 transfer
function (see the Transfer Function section).
Gain Error Match
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output frequency
obtained under a gain of 1. This gives the gain error observed
when the gain selection is changed from 1 to 2, 8, or 16.
Rev. A | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADE7755.PDF ] | |
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