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PDF AD9772 Data sheet ( Hoja de datos )
| Número de pieza | AD9772 | |
| Descripción | 14-Bit/ 150 MSPS TxDAC with 2x Interpolation Filter | |
| Fabricantes | Analog Devices | |
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a
14-Bit, 150 MSPS TxDAC+™
with 2؋ Interpolation Filter
AD9772
FEATURES
Single 2.7 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
150 MSPS Input Data Rate
63.3 MHz Reconstruction Passband @ 150 MSPS
75 dBc SFDR @ 25 MHz
2؋ Interpolation Filter with High or Low Pass Response
73 dB Image Rejection with 0.005 dB Passband Ripple
“Zero-Stuffing” Option for Enhanced Direct IF
Performance
Internal 2؋/4؋ Clock Multiplier
205 mW Power Dissipation; 13 mW with Power-Down
Mode
48-Lead LQFP Package
APPLICATIONS
Communication Transmit Channel
WCDMA Base Stations, Multicarrier Base Stations,
Direct IF Synthesis
Instrumentation
PRODUCT DESCRIPTION
The AD9772 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for baseband or IF waveform
reconstruction applications requiring exceptional dynamic range.
Manufactured on an advanced CMOS process, it integrates a
complete, low distortion 14-bit DAC with a 2× digital interpola-
tion filter and clock multiplier. The on-chip PLL clock multi-
plier provides all the necessary clocks for the digital filter and the
14-bit DAC. A flexible differential clock input allows for a single-
ended or differential clock driver for optimum jitter performance.
For baseband applications, the 2× digital interpolation filter
provides a low pass response, hence providing up to a three-fold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper inband
image by more than 73 dB. For direct IF applications, the 2×
digital interpolation filter response can be reconfigured to select
the upper inband image (i.e., high pass response) while sup-
pressing the original baseband image. To increase the signal
level of the higher IF images and their passband flatness in di-
rect IF applications, the AD9772 also features a “zero stuffing”
option in which the data following the 2× interpolation filter is
upsampled by a factor of two by inserting midscale data samples.
The AD9772 can reconstruct full-scale waveforms with band-
widths as high as 63.3 MHz while operating at an input data rate of
150 MSPS. The 14-bit DAC provides differential current out-
puts to support differential or single-ended applications. A
TxDAC+ is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD
MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
CLK+
CLK–
AD9772
CLOCK DISTRIBUTION
AND MODE SELECT
PLL CLOCK
MULTIPLIER
1؋ 1؋/2؋ FILTER
MUX 2؋/4؋
CONTROL CONTROL
PLLCOM
LPF
PLLVDD
DATA
INPUTS
(DB13...DB0)
SLEEP
EDGE-
TRIGGERED
LATCHES
2؋ FIR
INTERPOLATION
FILTER
ZERO
STUFF
MUX
14-BIT DAC
+1.2V REFERENCE
AND CONTROL AMP
IOUTA
IOUTB
REFIO
FSADJ
DCOM DVDD
ACOM AVDD
REFLO
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current out-
puts may be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an ap-
propriate resistive load.
The on-chip bandgap reference and control amplifier are config-
ured for maximum accuracy and flexibility. The AD9772 can be
driven by the on-chip reference or by a variety of external refer-
ence voltages. The full-scale current of the AD9772 can be
adjusted over a 2 mA to 20 mA range, thus providing additional
gain ranging capabilities.
The AD9772 is available in a 48-lead LQFP package and speci-
fied for operation over the industrial temperature range of –40°C
to +85°C.
PRODUCT HIGHLIGHTS
1. A flexible, low power 2× interpolation filter supporting re-
construction bandwidths of up to 63.3 MHz can be config-
ured for a low or high pass response with 73 dB of image
rejection for traditional baseband or direct IF applications.
2. A “zero-stuffing” option enhances direct IF applications.
3. A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.
4. The AD9772 digital interface, consisting of edge-triggered
latches and a flexible differential or single-ended clock input,
can support input data rates up to 150 MSPS.
5. On-chip PLL clock multiplier generates all of the internal high
speed clocks required by the interpolation filter and DAC.
6. The current output(s) of the AD9772 can easily be configured
for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
DIGITAL FILTER SPECIFICATIONS (TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V,
IOUTFS = 20 mA, Differential Transformer Coupled Output, 50 ⍀ Doubly Terminated, unless otherwise noted)
AD9772
Parameter
Min Typ Max
Units
MAXIMUM INPUT DATA RATE (fDATA)
DIGITAL FILTER CHARACTERISTICS
Passband Width1: 0.005 dB
Passband Width: 0.01 dB
Passband Width: 0.1 dB
Passband Width: –3 dB
LINEAR PHASE (FIR IMPLEMENTATION)
150
0.401
0.404
0.422
0.479
MSPS
fOUT/fDATA
fOUT/fDATA
fOUT/fDATA
fOUT/fDATA
STOPBAND REJECTION
0.606 fCLOCK to 1.394 fCLOCK
GROUP DELAY2
73 dB
21 Input Clocks
IMPULSE RESPONSE DURATION
–40 dB
–60 dB
36 Input Clocks
42 Input Clocks
NOTES
1Excludes sin(x)/x characteristic of DAC.
2Defined as the number of data clock cycles between impulse input and peak of output response.
Specifications subject to change without notice.
0
–20
–40
–60
–80
–100
–120
–140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
FREQUENCY – DC TO fDATA
0.8 0.9
1
Figure 2a. FIR Filter Frequency Response—Baseband Mode
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
5 10 15 20 25 30 35 40 45
TIME – Samples
Figure 2b. FIR Filter Impulse Response—Baseband Mode
Table I. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)
Lower
Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
Upper
Coefficient
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
Integer
Value
10
0
–31
0
69
0
–138
0
248
0
–419
0
678
0
–1083
0
1776
0
–3282
0
10364
16384
REV. 0
–5–
5 Page 
AD9772
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9772.
The AD9772 is a complete, 2× oversampling, 14-bit DAC that
includes a 2× interpolation filter, a phase-locked loop (PLL)
clock multiplier and a 1.20 V bandgap voltage reference. While
the AD9772’s digital interface can support input data rates as
high as 150 MSPS, its internal DAC can operate up to 400 MSPS,
thus providing direct IF conversion capabilities. The 14-bit
DAC provides two complementary current outputs whose full-
scale current is determined by an external resistor. The AD9772
features a flexible, low jitter, differential clock input providing
excellent noise rejection while accepting a sine wave input. An
on-chip PLL clock multiplier produces all of the necessary
synchronized clocks from an external reference clock source.
Separate supply inputs are provided for each functional block to
ensure optimum noise and distortion performance. A SLEEP
mode is also included for power savings.
CLKCOM CLKVDD
MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
CLK+
CLK–
AD9772
CLOCK DISTRIBUTION
AND MODE SELECT
PLL CLOCK
MULTIPLIER
1؋ 1؋/2؋ FILTER
MUX 2؋/4؋
CONTROL CONTROL
PLLCOM
LPF
PLLVDD
DATA
INPUTS
(DB13...DB0)
SLEEP
EDGE-
TRIGGERED
LATCHES
2؋ FIR
INTERPOLATION
FILTER
ZERO
STUFF
MUX
14-BIT DAC
+1.2V REFERENCE
AND CONTROL AMP
IOUTA
IOUTB
REFIO
FSADJ
DCOM DVDD
ACOM AVDD
REFLO
Figure 22. Functional Block Diagram
Preceding the 14-bit DAC is a 2× digital interpolation filter that
can be configured for a low pass (i.e., baseband mode) or high
pass (i.e., direct IF mode) response. The input data is latched
into the edge-triggered input latches on the rising edge of the
differential input clock as shown in Figure 1a and then interpo-
lated by a factor of two by the digital filter. For traditional base-
band applications, the 2× interpolation filter has a low pass
response. For direct IF applications, the filter’s response can be
converted into a high pass response to extract the higher image.
The output data of the 2× interpolation filter can update the
14-bit DAC directly or undergo a “zero-stuffing” process to
increase the DAC update rate by another factor of two. This
action enhances the relative signal level and passband flatness of
the higher images.
DIGITAL MODES OF OPERATION
The AD9772 features four different digital modes of operation
controlled by the digital inputs, MOD0 and MOD1. MOD0
controls the 2× digital filter’s response (i.e., low pass or high
pass), while MOD1 controls the “zero-stuffing” option. The
selected mode as shown in Table II will depend on whether the
application requires the reconstruction of a baseband or IF signal.
Table II. Digital Modes
Digital
Mode
Baseband
Baseband
Direct IF
Direct IF
MOD0
0
0
1
1
MOD1
0
1
0
1
Digital
Filter
Low
Low
High
High
Zero-
Stuffing
No
Yes
No
Yes
Applications requiring the highest dynamic range over a wide
bandwidth should consider operating the AD9772 in a baseband
mode. Note, the “zero-stuffing” option can also be used in this
mode although the ratio of signal to image power will be re-
duced. Applications requiring the synthesis of IF signals should
consider operating the AD9772 in a Direct IF mode. In this
case, the “zero-stuffing” option should be considered when
synthesizing and selecting IFs beyond the input data rate, fDATA.
If the reconstructed IF falls below fDATA, the “zero-stuffing”
option may or may not be beneficial. Note, the dynamic range
(i.e., SNR/SFDR) is also optimized by disabling the PLL Clock
Multiplier (i.e., PLLVDD to PLLCOM) and using an external
low jitter clock source operating at the DAC update rate, fDAC.
2؋ Interpolation Filter Description
The 2× interpolation filter is based on a 43-tap half-band sym-
metric FIR topology that can be configured for a low or high
pass response, depending on state of the MOD0 control input.
The low pass response is selected with MOD0 LOW while the
high pass response is selected with MOD0 HIGH. The low pass
frequency and impulse response of the half-band interpolation
filter are shown in Figures 2a and 2b, while Table I lists the
idealized filter coefficients. Note, a FIR filter’s impulse response
is also represented by its idealized filter coefficients.
The 2× interpolation filter essentially multiplies the input data
rate to the DAC by a factor of two, relative to its original input
data rate, while simultaneously reducing the magnitude of the
1st image associated with the original input data rate occurring
at fDATA – fFUNDAMENTAL. Note, as a result of the 2× interpola-
tion, the digital filter’s frequency response is uniquely defined
over its Nyquist zone of dc to fDATA, with mirror images occur-
ring in adjacent Nyquist zones.
The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to the 2× digital interpolation filter in a low
pass configuration. Images of the sine wave signal appear around
multiples of the DAC’s input data rate (i.e., fDATA) as predicted
by sampling theory. These undesirable images will also appear
at the output of a reconstruction DAC, although attenuated by
the DAC’s sin(x)/x roll-off response.
In many bandlimited applications, the images from the recon-
struction process must be suppressed by an analog filter follow-
ing the DAC. The complexity of this analog filter is typically
determined by the proximity of the desired fundamental to the
first image and the required amount of image suppression. Add-
ing to the complexity of this analog filter may be the require-
ment of compensating for the DAC’s sin(x)/x response.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9772.PDF ] | |
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