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AM28F256A-120EC Schematic ( PDF Datasheet ) - Advanced Micro Devices

Teilenummer AM28F256A-120EC
Beschreibung 256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt/ Bulk Erase Flash Memory with Embedded Algorithms
Hersteller Advanced Micro Devices
Logo Advanced Micro Devices Logo 




Gesamt 35 Seiten
AM28F256A-120EC Datasheet, Funktion
FINAL
Am28F256A
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s High performance
— Access times as fast as 70 ns
s CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
s Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s 100,000 write/erase cycles minimum
s Write and erase voltage 12.0 V ±5%
s Latch-up protected to 100 mA from –1 V to
VCC +1 V
s Embedded Erase Electrical Bulk Chip-Erase
— 1.5 seconds typical chip-erase including
pre-programming
s Embedded Program
— 14 µs typical byte-program including time-out
— 0.5 second typical chip program
s Command register architecture for
microprocessor/microcontroller compatible
write interface
s On-chip address and data latches
s Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s Embedded algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F256A is a 256 K Flash memory organized
as 32 Kbytes of 8 bits each. AMD’s Flash memories
offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F256A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in standard EPROM programmers. The
Am28F256A is erased when shipped from the factory.
The standard Am28F256A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F256A has separate chip enable (CE#)
and output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
Publication# 18879 Rev: C Amendment/+2
Issue Date: May 1998
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
nal electric fields for erase and programming
operations produces reliable cycling. The Am28F256A
uses a 12.0V± 5% VPP high voltage input to perform
the erase and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to VCC +1 V.
Embedded Program
The Am28F256A is byte programmable using the
Embedded Programming algorithm. The Embedded
Programming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F256A is one half second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are






AM28F256A-120EC Datasheet, Funktion
ORDERING INFORMATION
Standard Products
AM28F256A -70
J
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am28F256A
256 Kilobit (32 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms
Valid Combinations
AM28F256A-70
AM28F256A-90
AM28F256A-120
AM28F256A-150
AM28F256A-200
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
6 Am28F256A

6 Page









AM28F256A-120EC pdf, datenblatt
FLASH MEMORY PROGRAM/ERASE
OPERATIONS
Embedded Erase Algorithm
The automatic chip erase does not require the device
to be entirely pre-programmed prior to executing the
Embedded set-up erase command and Embedded
erase command. Upon executing the Embedded erase
command the device automatically will program and
verify the entire memory for an all zero data pattern.
The system is not required to provide any controls or
timing during these operations.
When the device is automatically verified to contain an
all zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operation are complete when
the data on DQ7 is “1" (see Write Operation Status sec-
tion) atwhich time the device returns to Read mode.
The system is not required to provide any control or
timing during these operations.
When using the Embedded Erase algorithm, the erase
automatically terminates when adequate erase margin
has been achieved for the memory array (no erase ver-
ify command is required). The margin voltages are in-
ternally generated in the same manner as when the
standard erase verify command is used.
The Embedded Erase Set-Up command is a command
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Embedded
Erase Setup is performed by writing 30h to the com-
mand register.
To commence automatic chip erase, the command 30h
must be written again to the command register. The au-
tomatic erase begins on the rising edge of the WE and
terminates when the data on DQ7 is “1" (see Write Op-
eration Status section) at which time the device returns
to Read mode.
Figure 1 and Table 4 illustrate the Embedded Erase al-
gorithm, a typical command string and bus operation.
START
Apply VPPH
Write Embedded Erase Setup Command
Write Embedded Erase Command
Data# Poll from Device
Erasure Completed
Figure 1. Embedded Erase Algorithm
18879C-6
Table 4. Embedded Erase Algorithm
Bus Operations
Command
Comments
Standby
Write
Read
Embedded Erase Setup Command
Embedded Erase Command
Wait for VPP Ramp to VPPH (see Note)
Data = 30h
Data = 30h
Data# Polling to Verify Erasure
Standby
Compare Output to FFh
Read
Available for Read Operations
Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or
switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer
to Functional Description.
12 Am28F256A

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