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PDF AM28F256A Data sheet ( Hoja de datos )
| Número de pieza | AM28F256A | |
| Descripción | 256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt/ Bulk Erase Flash Memory with Embedded Algorithms | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
Am28F256A
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s High performance
— Access times as fast as 70 ns
s CMOS low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
s Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s 100,000 write/erase cycles minimum
s Write and erase voltage 12.0 V ±5%
s Latch-up protected to 100 mA from –1 V to
VCC +1 V
s Embedded Erase Electrical Bulk Chip-Erase
— 1.5 seconds typical chip-erase including
pre-programming
s Embedded Program
— 14 µs typical byte-program including time-out
— 0.5 second typical chip program
s Command register architecture for
microprocessor/microcontroller compatible
write interface
s On-chip address and data latches
s Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s Embedded algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F256A is a 256 K Flash memory organized
as 32 Kbytes of 8 bits each. AMD’s Flash memories
offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F256A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in standard EPROM programmers. The
Am28F256A is erased when shipped from the factory.
The standard Am28F256A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F256A has separate chip enable (CE#)
and output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
Publication# 18879 Rev: C Amendment/+2
Issue Date: May 1998
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
nal electric fields for erase and programming
operations produces reliable cycling. The Am28F256A
uses a 12.0V± 5% VPP high voltage input to perform
the erase and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to VCC +1 V.
Embedded Program
The Am28F256A is byte programmable using the
Embedded Programming algorithm. The Embedded
Programming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F256A is one half second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
1 page  
CONNECTION DIAGRAMS (continued)
A11 1
A9 2
A8 3
A13 4
A14 5
NC 6
WE 7
VCC
8
VPP 9
NC 10
NC 11
A12 12
A7 13
A6 14
A5 15
A4 16
32-Pin — Standard Pinout
OE#
A10
CE#
D7
D6
D5
D4
D3
VSS
D2
D1
D0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin — Reverse Pinout
LOGIC SYMBOL
32 OE#
31 A10
30 CE#
29 D7
28 D6
27 D5
26 D4
25 D3
24 VSS
23 D2
22 D1
21 D0
20 A0
19 A1
18 A2
17 A3
32 A11
31 A9
30 A8
29 A13
28 A14
27 NC
26 WE#
25 VCC
24 VPP
23 NC
22 NC
21 A12
20 A7
19 A6
18 A5
17 A4 18879C-4
15
A0–A14
DQ0–DQ7
8
CE# (E#)
OE# (G#)
WE# (W#)
18879C-5
Am28F256A
5
5 Page 
ERASE, PROGRAM, AND READ MODE
When VPP is equal to 12.0 V ± 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High voltage must be applied to the VPP pin in order to
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an address-
able memory location. The register is a latch that stores
the command, along with the address and data infor-
mation needed to execute the command. The register
is written by bringing WE# and CE# to VIL, while OE#
is at VIH. Addresses are latched on the falling edge of
WE#, while data is latched on the rising edge of the
WE# pulse. Standard microprocessor write timings are
used.
The device requires the OE# pin to be VIH for write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be VIH, and CE# and WE#
must be VIL. If any pin is not in the correct state a write
command will not be executed.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the VPP pin. The device operates as a read only
memory. High voltage on the VPP pin enables the
command register. Device operations are selected by
writing specific data codes into the command register.
Table 3 in the device data sheet defines these register
commands.
Read Command
Memory contents can be accessed via the read com-
mand when VPP is high. To read from the device, write
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon VPP power-up. The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the VPP power
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
Table 3. Am28F256A Command Definitions
Command
Read Memory (Note 4)
First Bus Cycle
Operation
(Note 1)
Address
(Note 2)
Write
X
Data
(Note 3)
00h/FFh
Second Bus Cycle
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Read
RA
RD
Read Auto select
Embedded Erase Set-up/
Embedded Erase
Embedded Program Set-up/
Embedded Program
Reset (Note 4)
Write
Write
Write
Write
X
80h or 90h
Read
00h/01h
01h/2Fh
X
30h Write
X
30h
X
10h or 50h
Write
X
00h/FFh
Write
PA PD
X 00h/FFh
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
X = Don’t care.
3. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.
4. Please reference Reset Command section.
Am28F256A
11
11 Page | ||
| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet AM28F256A.PDF ] | |
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