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PDF AS7C1024-15JC Data sheet ( Hoja de datos )
| Número de pieza | AS7C1024-15JC | |
| Descripción | 5V/3.3V 128K8 CMOS SRAM (Evolutionary Pinout) | |
| Fabricantes | ETC | |
| Logotipo |  |
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November 2000
®
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
AS7C1024
AS7C31024
Features
• AS7C1024 (5V version)
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
• Low power consumption: ACTIVE
- 825 mW (c) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP I
- 8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
VCC
GND
Input buffer
A0
A1
A2
A3
512×256×8
A4 Array
A5
A6
(1,048,576)
A7
A8
Column decoder
Control
circuit
I/O7
I/O0
WE
OE
CE1
CE2
Pin arrangement
32-pin TSOP I
(8 x 20mm)
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
VCC
NC
8
9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
32
31
30
OE
A10
CE1
NC
A16
29 I/O7 A14
28 I/O6 A12
27 I/O5 A7
26 I/O4 A6
25 I/O3 A5
24
23
22
21
20
GND
I/O2
I/O1
I/O0
A0
A4
A3
A2
A1
19 A1
A0
18 A2 I/O0
17 A3 I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
Shaded areas contain advance information.
AS7C1024
AS7C31024
AS7C1024
AS7C31024
AS7C1024-10
AS7C31024-10
10
5
150
100
10
10
AS7C1024-12 AS7C1024-15 AS7C1024-20
AS7C31024-12 AS7C31024-15 AS7C31024-20
12 15 20
6 8 10
140 125 110
90 80 75
10 10 15
10 10 15
Unit
ns
ns
mA
mA
mA
mA
11/29/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
1 page  
AS7C1024
AS7C31024
®
Write cycle (over the operating range)
-10
Parameter
Symbol Min Max
Write cycle time
tWC 10 –
Chip enable (CE1) to write end
tCW1 9 –
Chip enable (CE2) to write end
tCW2 9 –
Address setup to write end
tAW 9 –
Address setup time
tAS 0 –
Write pulse width
tWP 7 –
Address hold from end of write
tAH 0 –
Data valid to write end
tDW 6 –
Data hold time
tDH 0 –
Write enable to output in high Z tWZ – 5
Output active from write end
tOW 3 –
Shaded areas contain advance information.
-12
Min Max
12 –
10 –
10 –
10 –
0–
8–
0–
6–
0–
–5
3–
-15
Min Max
15 –
12 –
12 –
12 –
0–
9–
0–
9–
0–
–5
3–
-20
Min Max
20 –
12 –
12 –
12 –
0–
12 –
0–
10 –
0–
–5
3–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
12
12
4, 5
4, 5
4, 5
Write waveform 1 ( WE controlled)
Address
tWC
tAW
WE
tAS
tWP
DIN
tWZ
DOUT
tAH
tDW
Data valid
tOW
tDH
Write waveform 2 (CE1 and CE2 controlled)
tWC
tAW
Address
tAS tCW1, tCW2
CE1
CE2
tWP
WE
tWZ tDW
DIN Data valid
DOUT
tAH
tDH
11/29/00 ALLIANCE SEMICONDUCTOR
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AS7C1024-15JC.PDF ] | |
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