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PDF CS8415A Data sheet ( Hoja de datos )
| Número de pieza | CS8415A | |
| Descripción | 96 kHz DIGITAL AUDIO INTERFACE RECEIVER | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CS8415A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CS8415A
96 kHz Digital Audio Interface Receiver
Features
! Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Receiver
! +5.0 V Analog Supply (VA+)
! +3.3 V or +5.0 V Digital Interface (VL+)
! 7:1 S/PDIF Input MUX
! Flexible 3-wire Serial Digital Output Port
! 8-kHz to 96-kHz Sample Frequency Range
! Low-jitter Clock Recovery
! Pin and Microcontroller Read Access to
Channel Status and User Data
! Microcontroller and Standalone Modes
! Differential Cable Receiver
! On-chip Channel Status and User Data Buffer
Memories
! Auto-detection of Compressed Audio Input
Streams
! Decodes CD Q Sub-Code
! OMCK System Clock Mode
General Description
The CS8415A is a monolithic CMOS device which re-
ceives and decodes one of 7 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3. The CS8415A has a serial digital audio output
port and comprehensive control ability through a 4-wire
microcontroller port. Channel status and user data are
assembled in block-sized buffers, making read access
easy.
A low-jitter clock recovery mechanism yields a very
clean recovered clock from the incoming AES3 stream.
Stand-alone operation allows systems with no micro-
controller to operate the CS8415A with dedicated
output pins for channel status data.
The CS8415A is available in a 28-pin TSSOP and SOIC
package in both Commerical (-10 to +70°C) and Indus-
trial grades (-40 to +85° C). The CDB8415A Customer
Demonstration board is also available for device evalu-
ation and implementation suggestions. Please refer to
page 2 for ordering information.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and
automotive audio systems.
VA+ AGND FILT RERR RMCK
VL+ DGND OMCK
RXN0
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
Receiver
Clock & AES3
Data
S/PDIF
Recovery Decoder
7:1
MUX
Misc.
Control
C & U bit
Data
Buffer
Control
Port &
Registers
Serial
Audio
Output
H/S RST EMPH U
SDA/ SCL/ AD1/ AD0/ INT
CDOUT CCLK CDIN CS
OLRCK
OSCLK
SDOUT
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
AUGUST '05
DS470F4
1 page  
CS8415A
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ................................................................................................... 8
Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 8
Figure 3. SPI Mode Timing .......................................................................................................................... 9
Figure 4. I²C Mode Timing ......................................................................................................................... 10
Figure 5. Recommended Connection Diagram for Software Mode ........................................................... 11
Figure 6. Serial Audio Output Example Formats........................................................................................ 14
Figure 7. AES3 ReceiverTiming for C & U Pin Output Data ...................................................................... 17
Figure 8. Control Port Timing in SPI Mode ................................................................................................ 18
Figure 9. Control Port Timing in I²C Mode ................................................................................................. 19
Figure 10. Hardware Mode ........................................................................................................................ 31
Figure 11. Professional Input Circuit .......................................................................................................... 36
Figure 12. Transformerless Professional Input Circuit ............................................................................... 36
Figure 13. Consumer Input Circuit ............................................................................................................. 36
Figure 14. S/PDIF MUX Input Circuit ......................................................................................................... 36
Figure 15. TTL/CMOS Input Circuit............................................................................................................ 36
Figure 16. Channel Status Data Buffer Structure....................................................................................... 37
Figure 17. Flowchart for Reading the E Buffer........................................................................................... 38
Figure 18. PLL Block Diagram ................................................................................................................... 40
Figure 19. Recommended Layout Example............................................................................................... 41
Figure 20. Jitter Tolerance Template ......................................................................................................... 43
Figure 21. Revision A................................................................................................................................. 44
Figure 22. Revision A1............................................................................................................................... 44
Figure 23. Revision A2 using A1 Values.................................................................................................... 44
Figure 24. Revision A2 using A2* Values .................................................................................................. 44
LIST OF TABLES
Table 1. Control Register Map Summary................................................................................................... 20
Table 2. Equivalent Software Mode Bit Definitions .................................................................................... 31
Table 3. Hardware Mode Start-Up Options................................................................................................ 31
Table 4. Second Line Part Marking............................................................................................................ 42
Table 5. Fs = 8 to 96 kHz ........................................................................................................................... 42
Table 6. Fs = 32 to 96 kHz ......................................................................................................................... 42
Table 7. Revision History ........................................................................................................................... 45
DS470F4
5
5 Page 
2. TYPICAL CONNECTION DIAGRAM
CS8415A
+5.0 V
Analog
Supply*
Ferrite *
Bead
0.1µF
0.1µF
+3.3 V or +5.0 V
Digital Supply
* * AES3/
SPDIF
Sources
Clock Control
Hardware
Control
VA+ VL+
RXP6 CS8415A
RXP5
OLRCK
RXP4
OSCLK
RXP3
RXP2
SDOUT
RXP1
RXP0
RXN0
SDA/CDOUT
RMCK
AD0/CS
SCL/CCLK
AD1/CDIN
INT
U
EMPH/AD 2
RERR
DGND2
RST
H/S
AGND FILT
DGND
3-wire Serial
Audio Input
Device
Microcontroller
RFILT
CFILT
CRIP
* A separate analog supply is only necessary in applications where RMCK is used
for a jitter sensitive task. For applications where RMCK is not used for a jitter
sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling
capacitor between VA+ and AGND.
* * Please see section 5.1 "7:1 S/PDIF Input Multiplexer" and Appendix A for typical
input configurations and recommended input circuits.
Figure 5. Recommended Connection Diagram for Software Mode
DS470F4
11
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| PDF Descargar | [ Datasheet CS8415A.PDF ] | |
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