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AC121 Schematic ( PDF Datasheet ) - Siemens Semiconductor Group

Teilenummer AC121
Beschreibung pnp germanium transistors
Hersteller Siemens Semiconductor Group
Logo Siemens Semiconductor Group Logo 




Gesamt 10 Seiten
AC121 Datasheet, Funktion
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
D AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54AC112 . . . F PACKAGE
CD74AC112 . . . E OR M PACKAGE
(TOP VIEW)
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
1
2
3
4
5
6
7
8
16 VCC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 2Q
description/ordering information
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74AC112E
CD74AC112E
–55°C to 125°C SOIC – M
Tube
CD74AC112M
Tape and reel CD74AC112M96
AC112M
CDIP – F
Tube
CD54AC112F3A
CD54AC112F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1






AC121 Datasheet, Funktion
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
R1 = 500 S1
R2 = 500
2 × VCC
Open
GND
When VCC = 1.5 V, R1 = R2 = 1 k
LOAD CIRCUIT
Input
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCC
GND
tw
50% VCC
VCC
50% VCC
0V
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
CLK
50% VCC
trec
50% VCC
VOLTAGE WAVEFORMS
RECOVERY TIME
VCC
0V
VCC
0V
Reference
Input
50% VCC
VCC
0V
Data
Input
50%
10%
tsu
90%
tr
th
90%
VCC
5100%%VC0CV
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
Input
In-Phase
Output
Out-of-Phase
Output
50% VCC
tPLH
50%
10%
tPHL
90%
90%
50% VCC
tPHL
90%
tr
501%0%VCC
tf
tPLH
50%
10%
VCC
0V
VOH
5100%%VCVCOL
tf
90% VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
Output
Control
50% VCC
VCC
50% VCC
0V
tPZL
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZH
50% VCC
50% VCC
tPLZ
VCC
20% VCC
VOL
tPHZ
VOH
80% VCC
0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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