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AB28F200BX-T90 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer AB28F200BX-T90
Beschreibung 2-MBIT (128K x 16/ 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
AB28F200BX-T90 Datasheet, Funktion
A28F200BX-T B
2-MBIT (128K x 16 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
Automotive
Y x8 x16 Input Output Architecture
A28F200BX-T A28F200BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Y Optimized High Density Blocked
Architecture
One 16 KB Protected Boot Block
Two 8 KB Parameter Blocks
One 96 KB Main Block
One 128 KB Main Block
Top or Bottom Boot Locations
Y Extended Cycling Capability
1 000 Block Erase Cycles
Y Automated Word Byte Write and
Block Erase
Command User Interface
Status Register
Erase Suspend Capability
Y SRAM-Compatible Write Interface
Y Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Very High-Performance Read
90 ns Maximum Access Time
45 ns Maximum Output Enable Time
Y Low Power Consumption
25 mA Typical Active Read Current
Y Deep Power-Down Reset Input
Acts as Reset for Boot Operations
Y Automotive Temperature Operation
b40 C to a125 C
Y Write Protection for Boot Block
Y Industry Standard Surface Mount
Packaging
JEDEC ROM Compatible
44-Lead PSOP
Y 12V Word Byte Write and Block Erase
VPP e 12V g5% Standard
Y ETOXTM III Flash Technology
5V Read
Y Independent Software Vendor Support
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290500-003






AB28F200BX-T90 Datasheet, Funktion
A28F200BX-T B
1 3 Pinouts
The A28F200BX 44-Lead PSOP pinout follows the
industry standard ROM EPROM pinout as shown in
Figure 2 with an upgrade to the 28F400BC (4-Mbit
flash family)
A28F400BX
VPP
DU
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
290500 – 3
Figure 2 PSOP Lead Configuration
A28F400BX
RP
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
DQ15 Ab1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
6

6 Page









AB28F200BX-T90 pdf, datenblatt
A28F200BX-T B
3 2 1 1 Output Control
With OE at logic-high level (VIH) the output from
the device is disabled and data input output pins
(DQ 0 15 or DQ 0 7 ) are tri-stated Data input is
then controlled by WE
3 2 1 2 Input Control
With WE at logic-high level (VIH) input to the de-
vice is disabled Data Input Output pins (DQ- 0 15
or DQ 0 7 ) are controlled by OE
3 2 2 INTELLIGENT IDENTlFlERS
The manufacturer and device codes are read via the
CUI or by taking the A9 pin to 12V Writing 90H to
the CUI places the device into Intelligent Identifier
read mode A read of location 00000H outputs the
manufacturer’s identification code 0089H and loca-
tion 00001H outputs the device code 2274H for
A28F200BX-T 2275H for A28F200BX-B When
BYTE is at a logic low only the lower byte of the
above signatures is read and DQ15 Ab1 is a ‘‘don’t
care’’ during Intelligent Identifier mode A read array
command must be written to the CUI to return to the
read array mode
3 3 Write Operations
Commands are written to the CUI using standard mi-
croprocessor write timings The CUl serves as the
interface between the microprocessor and the inter-
nal chip operation The CUI can decipher Read Ar-
ray Read Intelligent Identifier Read Status Register
Clear Status Register Erase and Program com-
mands In the event of a read command the CUI
simply points the read path at either the array the
Intelligent Identifier or the status register depending
on the specific read command given For a program
or erase cycle the CUI informs the write state ma-
chine that a write or erase has been requested Dur-
ing a program cycle the Write State Machine will
control the program sequences and the CUI will only
respond to status reads During an erase cycle the
CUI will respond to status reads and erase suspend
After the Write State Machine has completed its
task it will allow the CUI to respond to its full com-
mand set The CUI will stay in the current command
state until the microprocessor issues another com-
mand
The CUI will successfully initiate an erase or write
operation only when VPP is within its voltage range
Depending upon the application the system design-
er may choose to make the VPP power supply
switchable available only when memory updates
are desired The system designer can also choose
to ‘‘hard-wire’’ VPP to 12V The 2-Mbit boot block
flash family is designed to accommodate either de-
sign practice It is strongly recommended that RP
be tied to logical Reset for data protection during
unstable CPU reset function as described in the
‘‘Product Family Overview’’ section
3 3 1 BOOT BLOCK WRITE OPERATIONS
In the case of Boot Block modifications (write and
erase) RP is set to VHH e 12V typically in addi-
tion to VPP at high voltage However if RP is not at
VHH when a program or erase operation of the boot
block is attempted the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase refer to
Table 4 for Status Register Definitions) is set to indi-
cate the failure to complete the operation
3 3 2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor The CUI points the
read write path to the appropriate circuit block as
described in the previous section After the WSM
has completed its task it will set the WSM Status bit
to a ‘‘1’’ which will also allow the CUI to respond to
its full command set Note that after the WSM has
returned control to the CUI the CUI will remain in its
current state
3 3 2 1 Command Set
Command
Codes
Device Mode
00 Invalid Reserved
10 Alternate Program Setup
20 Erase Setup
40 Program Setup
50 Clear Status Register
70 Read Status Register
90 Intelligent Identifier
B0 Erase Suspend
D0 Erase Resume Erase Confirm
FF Read Array
3 3 2 2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI Table 3 defines the 2-Mbit
boot block flash family commands
12

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