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AD2S93 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD2S93
Beschreibung Low Cost LVDT-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD2S93 Datasheet, Funktion
a
FEATURES
Full Function Monolithic LVDT-to-Digital Converter
Absolute Serial Data Output
Uncommitted Differential Input
Repeatability
Remote Diagnostics
14-Bit Resolution
Industrial Temperature Range
28-Pin PLCC
Low Power
APPLICATIONS
Industrial Gauging
Industrial Process Control
Linear Positioning Systems
Linear Actuator Control
Automotive Motion Sensing and Control
Torque Sensing Conditioner
AC Strain Gages Conditioning
Avionics
Low Cost
LVDT-to-Digital Converter
AD2S93
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
(PRIMARY
EXCITATION)
REF
DIFFERENTIAL
(SECONDARY A
VOLTAGE) B
R4 GAIN
DIFF
R3 LOS
VDD
OVR
UNR
NULL
CS
ACERROR
C3 C4 R5
R6 DEMODIN
ERROR
AMP
AC RATIO
BRIDGE
PHASE
SENSITIVE
DEMODULATOR
DEMOD OUT
R1 R7
INTIN
LOS
DECODE
LOGIC
UP-DOWN
COUNTER
LATCHES
FREQUENCY
SHAPING
VCO
C1 R2
C2
VEL
VCO GAIN
DIR
CLKOUT
DATA
SCLK
SERIAL
INTERFACE
AD2S93
GENERAL DESCRIPTION
The AD2S93 is a complete 14-bit resolution tracking LVDT-to-
digital converter. A Type II tracking loop is employed to track
the A–B input and produce a digital output equal to (A–B)/
(REF/2), where REF is a fixed amplitude ac reference phase co-
herent with the A–B input. This allows the measurement of any
2-, 3-, 4- and 5-wire LVDT or linear amplitude modulated in-
put. The operating frequency range is from 360 Hz to 10 kHz
with user definable bandwidth set externally within a range of
45 Hz to 1250 Hz.
The AD2S93 has a 16-bit serial output. The MSB (LOS), read
first, indicates a loss of the signal A, B, or reference inputs to the
converter or transducer. The second and third MSBs are flags
indicating whether [–REF/2 (UNR) A–B +REF/2 (OVR]) is
outside the linear operating range of the converter. The dis-
placement data is presented as 13-bit offset binary giving a ± 12-
bit operating range. LOS, OVR and UNR are pinned out on
the device, in addition a NULL flag is available which is set
when (A–B) = 0.
Absolute displacement information is accessed when CS is taken
LO followed by the application of an external clock (SCLK)
with a maximum rate of 2 MHz. Data is read MSB first. When
CS is high the DATA output is high impedance; this allows
daisy chaining of more than one converter onto a common bus.
The A, B differential input allows the user to scale the A, B in-
puts between 1 and 10. This enables the user to accurately set
up the inputs matching the REF input to the DIFF output. The
DIFF output is the resultant A–B. The AD2S93 operates using
± 5 V ± 5% power supplies and is fabricated on Analog Devices’
linear compatible CMOS process (LC2MOS). The (LC2MOS)
is a mixed technology process that combines precision bipolar
circuits with low power logic.
PRODUCT HIGHLIGHTS
Complete LVDT-to-Digital Interface. The AD2S93 pro-
vides the complete solution for digitizing LVDT signals to 14-
bit resolution.
Serial 16-Bit Output Data. One 16-bit read from the
AD2S93 determines input signal continuity (LOS), over and
underrange detection and 13 bits of offset binary displacement
information.
High Accuracy Grade in Low Cost Package. 0.05% and
0.1% integral linearity over the full –40°C to +85°C operating
temperature range.
Uncommitted Differential Input. Allows configuration of 2-,
3-, 4- and 5-wire LVDTs.
Multiple Converter Interfacing. High impedance data out-
put and a simple three-wire interface reduces cabling and elimi-
nates bus contention.
Low Power. 70 mW power consumption (typ).
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD2S93 Datasheet, Funktion
AD2S93
LOS
OVR
UNR
SIGN
0100
0100
0100
0000
0000
0001
0001
0001
0001
0011
0011
0011
OUTPUT CODES
MAGNITUDE
0000
0000
1111
0000
0000
1111
0000
0000
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
1111
0000
0000
1111
1111
0000
1111
0000
0001
+VE POSITION
FULL SCALE
1111
0000
0001
NULL
POSITION
1110
1111
0000
0001
–VE POSITION
FULL SCALE
1111
A – B = + REF/2
A–B=0
A – B = – REF/2
UNDER-
RANGE
–1
RANGE
OVER-
RANGE
0 ≠1
RATIO OF A- B/REF/2
Figure 2. Output Code Format
If the maximum operating stroke of an LVDT yielded a 1 V rms
A–B output, the weighting of the LVDT to AD2S93 digital out-
put would be:
Input Signal Full Scale
Full-Scale Operating Range (± 212 )
1×2 2
213
Input Scaling = 345 µV/LSB
This can be equated directly to the LVDT sensitivity specifica-
tion in mm/v/v.
Note: The overrange and underrange quadrants can be utilized
by decoding the overrange and underrange MSBs and decoding
the 12 magnitude bits. This will increase the operating range of
the AD2S93 accordingly. However, if the input A–B > VREF
then the converter will lose track of the input and will only re-
gain track when the input signal returns to within the operating
range of the converter.
INPUT GAIN
Since the transformation ratio of an LVDT or RVDT from exci-
tation voltage to signal voltage can be 1:0.15, provision for gain
scaling has been provided. The gain can, therefore, be selected
to ensure that the full-scale output of converter represents the
maximum stroke position of the transducer.
The gain setting is accomplished by connecting Pin 2, (DIFF)
and Pin 3 (GAIN) together (unity gain) or connecting two resis-
tors as shown in Figure 3.
The gain of the input stage is calculated using the following
equation:
DIFF ( A B) = 1 + R3
( A B) IN
R4
e.g., For a gain of 5, R3 = 12 k, R4 = 3 k
For a gain of 10, R3 = 18 k, R4 = 2 k
A
B
AGND
R4
GAIN
R3
DIFF
Figure 3. Pre-Amp Gain Block
SETTING THE CONVERTER BANDWIDTH
The AD2S93 bandwidth is set by placing three external compo-
nents, C1, C2, and R2, around the integrator as illustrated by
the figure below.
C1
R2
C2
THI R1
INT
CV
RV
VCO
62.5
THO
Figure 4. Integrator and VCO
Before the bandwidth can be set, the corresponding VCO gain
setting must be determined. The VCO gain is directly related to
the slew rate of the converter. This is set internally to two dif-
ferent rates defined internally by RV.
Typical converter slew rates are defined below,
G (1) = 2400 LSB/msMode 1
G (2) = 800 LSB/msMode 2
–6– REV. A

6 Page









AD2S93 pdf, datenblatt
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
P-28A
0.048 (1.21)
0.042 (1.07)
0.050
(1.27)
BSC
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
4
5
PIN 1
IDENTIFIER
26
25
TOP VIEW
0.020
(0.50)
R
11
12
19
18
0.456 (11.58)
0.450 (11.43) SQ
0.495 (12.57)
0.485 (12.32) SQ
0.180 (4.57)
0.165 (4.19)
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33)
0.430 (10.92)
0.390 (9.91)
0.032 (0.81)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
–12–

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