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AD2S90 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD2S90
Beschreibung Complete 12-Bit Resolver-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD2S90 Datasheet, Funktion
a
FEATURES
Complete Monolithic Resolver-to-Digital Converter
Incremental Encoder Emulation (1024-Line)
Absolute Serial Data (12-Bit)
Differential Inputs
12-Bit Resolution
Industrial Temperature Range
20-Lead PLCC
Low Power (50 mW)
APPLICATIONS
Industrial Motor Control
Servo Motor Control
Industrial Gauging
Encoder Emulation
Automotive Motion Sensing and Control
Factory Automation
Limit Switching
Low Cost, Complete 12-Bit
Resolver-to-Digital Converter
SIN
SIN LO
COS
COS LO
NMC
A
B
NM
CS
SCLK
DATA
AD2S90
FUNCTIONAL BLOCK DIAGRAM
REF
HIGH ACCURACY
ANGLE
SIN COS
MULTIPLIER
DECODE
LOGIC
DIGITAL
ANGLE
UP-DOWN
COUNTER
SIN ()
P.S.D. AND
FREQUENCY
SHAPING
ERROR
AMPLIFIER
VEL
U/D
CLK
CLKOUT
HIGH
DYNAMIC
RANGE V.C.O. DIR
LATCH
SERIAL INTERFACE
GENERAL DESCRIPTION
The AD2S90 is a complete 12-bit resolution tracking resolver-
to-digital converter. No external components are required to
operate the device.
The converter accepts 2 V rms ± 10% input signals in the range
3 kHz–20 kHz on the SIN, COS and REF inputs. A Type II
servo loop is employed to track the inputs and convert the input
SIN and COS information into a digital representation of the
input angle. The bandwidth of the converter is set internally at
1 kHz within the tolerances of the device. The guaranteed maxi-
mum tracking rate is 500 rps.
Angular position output information is available in two forms,
absolute serial binary and incremental A quad B.
The absolute serial binary output is 12-bit (1 in 4096). The data
output pin is high impedance when Chip Select CS is logic HI.
This allows the connection of multiple converters onto a com-
mon bus. Absolute angular information in serial pure binary
form is accessed by CS followed by the application of an exter-
nal clock (SCLK) with a maximum rate of 2 MHz.
The encoder emulation outputs A, B and NM continuously
produce signals equivalent to a 1024 line encoder. When de-
coded this corresponds to 12 bits of resolution. Three common
north marker pulsewidths are selected via a single pin (NMC).
An analog velocity output signal provides a representation of
velocity from a rotating resolver shaft traveling in either a clock-
wise or counterclockwise direction.
The AD2S90 operates on ± 5 V dc ± 5% power supplies and is
fabricated on Analog Devices’ Linear Compatible CMOS pro-
cess (LC2MOS). LC2MOS is a mixed technology process that
combines precision bipolar circuits with low power CMOS logic
circuits.
PRODUCT HIGHLIGHTS
Complete Resolver-Digital Interface. The AD2S90 provides
the complete solution for digitizing resolver signals (12-bit reso-
lution) without the need for external components.
Dual Format Position Data. Incremental encoder emulation
in standard A QUAD B format with selectable North Marker
width. Absolute serial 12-bit angular binary position data
accessed via simple 3-wire interface.
Single High Accuracy Grade in Low Cost Package. ±10.6 arc
minutes of angular accuracy available in a 20-lead PLCC.
Low Power. Typically 50 mW power consumption.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






AD2S90 Datasheet, Funktion
AD2S90
ABSOLUTE POSITION OUTPUT
SERIAL INTERFACE
Absolute angular position is represented by serial binary data
and is extracted via a three-wire interface, DATA, CS and
SCLK. The DATA output is held in a high impedance state
when CS is HI.
Upon the application of a Logic LO to the CS pin, the DATA
output is enabled and the current angular information is trans-
ferred from the counters to the serial interface. Data is retrieved
by applying an external clock to the SCLK pin. The maximum
data rate of the SCLK is 2 MHz. To ensure secure data retrieval
it is important to note that SCLK should not be applied until a
minimum period of 600 ns after the application of a Logic LO
to CS. Data is then clocked out, MSB first, on successive nega-
tive edges of the SCLK; 12 clock edges are required to extract
the full 12 bits of data. Subsequent negative edges greater than
the defined resolution of the converter will clock zeros from the
data output if CS remains in a low state.
If a resolution of less than 12 bits is required, the data access
can be terminated by releasing CS after the required number of
bits have been read.
t2 t6
CSB
t3
SCLK
t4 t*
DATA
MSB
LSB
t1 t5
t7
*THE MINIMUM ACCESS TIME: USER DEPENDENT
Figure 6. Serial Read Cycle
CS can be released a minimum of 100 ns after the last negative
edge. If the user is reading data continuously, CS can be reap-
plied a minimum of 250 ns after it is released (see Figure 6).
The maximum read time is given by: (12-bits read @ 2 MHz)
Max RD Time = [600 + (12 × 500) + 600 + 100] = 7.30 µs.
INCREMENTAL ENCODER OUTPUTS
The incremental encoder emulation outputs A, B and NM are
free running and are always valid, providing that valid resolver
format input signals are applied to the converter.
The AD2S90 emulates a 1024-line encoder. Relating this to
converter resolution means one revolution produces 1024 A, B
pulses. B leads A for increasing angular rotation (i.e., clockwise
direction). The addition of the DIR output negates the need for
external A and B direction decode logic. DIR is HI for increas-
ing angular rotation.
The north marker pulse is generated as the absolute angular
position passes through zero. The AD2S90 supports the three
industry standard widths controlled using the NMC pin. Figure
7 details the relationship between A, B and NM. The width of
NM is defined relative to the A cycle.
INCREASING ANGLE
A
B
90؇
*NM 180؇
360؇
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
*SELECTABLE WITH THREE - LEVEL
CONTROL PIN "MARKER" DEFAULT
TO 90؇ USING INTERNAL PULL - UP.
LEVEL
+VDD
0
–VSS
WIDTH
90؇
180؇
360؇
Figure 7. A, B and NM Timing
Unlike incremental encoders, the AD2S90 encoder output is
not subject to error specifications such as cycle error, eccentric-
ity, pulse and state width errors, count density and phase φ.
The maximum speed rating, n, of an encoder is calculated from
its maximum switching frequency, fMAX, and its ppr (pulses per
revolution).
n
=
60
× f MAX
PPR
The AD2S90 A, B pulses are initiated from CLKOUT which
has a maximum frequency of 2.048 MHz. The equivalent
encoder switching frequency is:
1/4 × 2.048 MHz = 512 kHz (4 updates = 1 pulse)
At 12 bits the ppr = 1024, therefore the maximum speed, n, of
the AD2S90 is:
n = 60 × 512000 = 30000 rpm
1024
This compares favorably with encoder specifications where fMAX
is specified from 20 kHz (photo diodes) to 125 kHz (laser based)
depending on the light system used. A 1024 line laser-based
encoder will have a maximum speed of 7300 rpm.
The inclusion of A, B outputs allows the AD2S90 + resolver
solution to replace optical encoders directly without the need to
change or upgrade existing application software.
–6– REV. D

6 Page









AD2S90 pdf, datenblatt
AD2S90
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
P-20A
20-Lead Plastic Leaded Chip Carrier (PLCC)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.042 (1.07)
3 19
4 PIN 1 18
IDENTIFIER
TOP VIEW
(PINS DOWN)
8 14
9 13
0.050
(1.27)
BSC
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.02)
0.385 (9.78)SQ
0.180 (4.57)
0.165 (4.19)
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
0.020
(0.50)
R
PIN 1
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
–12–
REV. D

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