PDF AD2S83 Data sheet ( Hoja de datos )

Número de pieza	AD2S83
Descripción	Resolver-to-Digital Converter
Fabricantes	Analog Devices
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No Preview Available ! a Variable Resolution, Resolver-to-Digital Converter AD2S83 FEATURES Tracking R/D Converter FUNCTIONAL BLOCK DIAGRAM High Accuracy Velocity Output High Max Tracking Rate 1040 RPS (10 Bits) 44-Lead PLCC Package 10-, 12-, 14-, or 16-Bit Resolution Set by User Ratiometric Conversion Stabilized Velocity Reference Dynamic Performance Set by User Industrial Temperature Range APPLICATIONS DC and AC Servo Motor Control SIN SIG GND COS A1 SEGMENT SWITCHING A2 HF FILTER REFERENCE I/P C3 OFFSET ADJUST R9 +12V –12V C1 R1 AC ERROR O/P R – 2R DAC A3 R2 R3 C2 R4 R8 BANDWIDTH SELECTION DEMOD O/P INTEGRATOR I/P C5 R5 C4 PHASE SENSITIVE DETECTOR INTEGRATOR O/P VELOCITY SIGNAL Process Control Numerical Control of Machine Tools Robotics Axis Control GND RIPPLE CLOCK +12V –12V 16-BIT UP/DOWN COUNTER OUTPUT DATA LATCH DATA SC1 SC2 ENABLE LOAD 16 DATA BITS AD2S83 VCO + DATA TRANSFER LOGIC VCO I/P VCO O/P BYTE 5V DIG BUSY DIRECTION INHIBIT SELECT GND R6 TRACKING RATE SELECTION C7 R7 3K3 C6 390pF GENERAL DESCRIPTION The AD2S83 is a monolithic 10-, 12-, 14-, or 16-bit tracking resolver-to-digital converter. The converter allows users to select their own resolution and dynamic performance with external components. The converter allows users to select the resolution to be 10, 12, 14, or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. The AD2S83 converts resolver format input signals into a paral- lel natural binary digital word using a ratiometric tracking con- version method. This ensures high noise immunity and tolerance of long leads allowing the converter to be located remote from the resolver. The position output from the converter is presented via 3-state output pins which can be configured for operations with 8- or 16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins ensure easy data transfer to 8- and 16-bit data bus, and outputs are provided to allow for cycle or pitch counting in external counters. A precise analog signal proportional to velocity is also available and will replace a tachogenerator. The AD2S83 operates over reference frequencies in the range 0 Hz to 20,000 Hz. PRODUCT HIGHLIGHTS High Accuracy Velocity Output. A precision analog velocity signal with a typical linearity of ± 0.1% and reversion error less than ± 0.3% is generated by the AD2S83. The provision of this signal removes the need for mechanical tachogenerators used in servo systems to provide loop stabilization and speed control. Resolution Set by User. Two control pins are used to select the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allow- ing optimum resolution for each application. Ratiometric Tracking Conversion. This technique provides continuous output position data without conversion delay. It also provides noise immunity and tolerance of harmonic distor- tion on the reference and input signals. Dynamic Performance Set by the User. By selecting external resistor and capacitor values the user can determine band- width, maximum tracking rate and velocity scaling of the converter to match the system requirements. The component values are easy to select using the free component selection software design aid. MODELS AVAILABLE Information on the models available is given in the Ordering Guide. REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page AD2S83–SPECIFICATIONS (؎VS = ؎12 V dc ؎ 5%; VL = 5 V dc ؎ 10%; TA = –40؇C to +85؇C) Parameter THREE-STATE LEAKAGE Current IL RATIO MULTIPLIER AC Error Output Scaling PHASE SENSITIVE DETECTOR Output Offset Voltage Gain In Phase In Quadrature Input Bias Current Input Impedance Input Voltage Conditions DB1–DB16 Only ± VS = ± 12.0 V, VL = 5.5 V VOL = 0 V ± VS = ± 12.0 V, VL = 5.5 V VOH = 5.0 V 10 Bit 12 Bit 14 Bit 16 Bit w.r.t. REF w.r.t. REF Min –0.882 1.0 Typ Max ؎20 ؎20 177.6 44.4 11.1 2.775 –0.9 60 12 –0.918 ± 0.02 150 ±8 INTEGRATOR Open-Loop Gain Dead Zone Current (Hysteresis) Input Offset Voltage Input Bias Current Output Voltage Range At 10 kHz 57 60 63 90 100 110 15 60 150 ؎8 VCO Maximum Rate VCO Rate VCO Power Supply Sensitivity Rate Input Offset Voltage Input Bias Current Input Bias Current Tempco Linearity of Absolute Rate AD2S83AP 0 kHz–500 kHz 0.5 MHz–1 MHz AD2S83IP 0 kHz–500 kHz 0.5 MHz–1 MHz Reversion Error AD2S83AP AD2S83IP +ve DIR –ve DIR +VS –VS 1.1 8.25 8.50 8.75 8.25 8.50 8.75 3 12 +0.22 +0.5 –0.5 50 ± 0.15 ± 0.25 ± 0.25 ± 0.25 ± 0.5 ± 1.0 ؎0.25 ؎1.0 ؎0.5 ؎1.0 ؎1.0 ؎1.5 POWER SUPPLIES Voltage Levels +VS –VS +VL Current ± IS ± IS ± IL ± VS @ ± 12 V ± VS @ ± 12.6 V +VL @ ± 5.0 V +11.4 –11.4 +4.5 +12.6 –12.6 +5 +VS ± 12 ± 19 ± 0.5 ؎23 ؎30 ؎1.5 All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. Unit µA µA mV/Bit mV/Bit mV/Bit mV/Bit mV V rms/V dc V rms/V dc nA MΩ V dB nA/LSB mV nA V MHz kHz/µA kHz/µA %/V %/V mV nA nA/°C % FSR % FSR % FSR % FSR % Output % Output V V V mA mA mA Model AD2S83AP AD2S83IP Temperature Range –40°C to +85°C –40°C to +85°C ORDERING GUIDE Accuracy 8 arc min 8 arc min Package Description Package Option Plastic Leaded Chip Carrier P-44A Plastic Leaded Chip Carrier P-44A –4– REV. E 5 Page AD2S83 BUSY RIPPLE CLOCK VH t1 t2 VH t4 VH DATA INHIBIT VH VH DIR INHIBIT ENABLE t6 t7 VL t8 VL DATA VZ t5 VL t9 VL t10 t11 BYTE SELECT VL VL t3 VH VL VH DATA t12 Figure 3. Digital Timing t13 VH VL Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ns TMIN 150 10 470 16 3 70 485 515 – 40 35 60 60 TMAX* 350 25 580 45 25 140 625 670 490 110 110 140 125 Condition BUSY WIDTH VH–VH RIPPLE CLOCK VH to BUSY VH RIPPLE CLOCK VL to Next BUSY VH BUSY VH to DATA VH BUSY VH to DATA VL INHIBIT VH to BUSY VH MIN DIR VH to BUSY VH MIN DIR VH to BUSY VH INHIBIT VL to DATA STABLE ENABLE VL to DATA VH ENABLE VL to DATA VL BYTE SELECT VL to DATA STABLE BYTE SELECT VH to DATA STABLE –10– REV. E 11 Page

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