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AD2S1200 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD2S1200
Beschreibung 12-Bit R/D Converter with Reference Oscillator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD2S1200 Datasheet, Funktion
12-Bit R/D Converter
with Reference Oscillator
AD2S1200
FEATURES
Complete monolithic R/D converter
Parallel and serial 12-bit data ports
System fault detection
Absolute position and velocity outputs
Differential inputs
±11 arc minutes of accuracy
1,000 rps maximum tracking rate, 12-bit resolution
Incremental encoder emulation (1,024 pulses/rev)
Programmable sinusoidal oscillator on-board
Compatible with DSP and SPI® interface standards
204.8 kHz square wave output
Single-supply operation (5.00 V ± 5%)
40°C to +125°C temperature rating
44-lead LQFP package
4 kV ESD protection
GENERAL DESCRIPTION
The AD2S1200 is a complete 12-bit resolution tracking resolver-
to-digital converter, integrating an on-board programmable
sinusoidal oscillator that provides sine wave excitation for
resolvers. An external 8.192 MHz crystal is required to provide
a precision time reference. This clock is internally divided to
generate a 4.096 MHz clock to drive all the peripherals.
The converter accepts 3.6 V p-p ± 10% input signals, in the
range of 10 kHz to 20 kHz on the Sin and Cos inputs. A Type II
servo loop is employed to track the inputs and convert the input
Sin and Cos information into a digital representation of the
input angle and velocity. The bandwidth of the converter is set
internally to 1.7 kHz with an external 8.192 MHz crystal. The
maximum tracking rate is 1,000 rps.
FUNCTIONAL BLOCK DIAGRAM
REFBYP REFOUT
FS1 FS2
CLKIN
XTALOUT (8.192MHz)
EXC
EXC
SinLO
Sin
CosLO
Cos
A
B
NM
SAMPLE
AD2S1200
VOLTAGE
REFERENCE
(4.096MHz)
INTERNAL
CLOCK
GENERATOR
REFERENCE
OSCILLATOR
(DAC)
(204.8kHz)
CLOCK
DIVIDER
SYNTHETIC
REFERENCE
FAULT
INDICATORS
ADC
ANGLE θ
ADC
ERROR
MONITOR
MONITOR
CALCULATION/
SIGNAL
ERROR
DEMODULATOR ERROR
MONITOR
ANGLE φ
DIGITAL
FILTER
ENCODER
EMULATION
POSITION
INTEGRATOR
VELOCITY
INTEGRATOR
CPO
DOS
LOT
DIR
POSITION REGISTER
VELOCITY REGISTER
MULTIPLEXER
DATA BUS OUTPUT
CS
RD
RESET RDVEL SOE
DB11
SO
DB10
SCLK
Figure 1.
DB9–DB0
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.






AD2S1200 Datasheet, Funktion
AD2S1200
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage (VDD)
Supply Voltage (AVDD)
Input Voltage
Output Voltage Swing
Operating Temperature Range (Ambient)
−0.3 V to +7.0 V
−0.3 V to + 7.0 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 24

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AD2S1200 pdf, datenblatt
AD2S1200
ABSOLUTE POSITION AND VELOCITY OUTPUT
The angular position and angular velocity are represented by
binary data and can be extracted either via a 12-bit parallel
interface or a 3-wire serial interface that operates at clock rates
up to 25 MHz. The chip select pin, CS, must be held low to
enable the device. Angular position and velocity can be selected
using a dedicated polarity input, RDVEL.
SOE Input
The serial output enable pin, SOE, is held high to enable the
parallel interface. The SOE pin is held low to enable the serial
interface, which places pins (DB0–DB9) in the high impedance
state, while DB11 is the serial output (SO), and DB10 is the
serial clock input (SCLK).
Data Format
The digital angle signal represents the absolute position of the
resolver shaft as a 12-bit unsigned binary word. The digital
velocity signal is a 12-bit twos complement word, which
represents the velocity of the resolver shaft rotating in either a
clockwise or a counterclockwise direction.
Finally, the RD input is used to read the data from the output
register and to enable the output buffer. The timing
requirements for the read cycle are illustrated in Figure 7.
SAMPLE Input
Data is transferred from the position and velocity integrators
respectively to the position and velocity registers following a
high to low transition of the SAMPLE signal. This pin must be
held low for at least t1 ns to guarantee correct latching of the
data. RD should not be pulled low before this time. Also, a
rising edge of SAMPLE resets the internal registers that contain
the minimum and maximum magnitude of the monitor signal.
PARALLEL INTERFACE
The angular position and angular velocity are available on the
AD2S1200 in two 12-bit registers, which can be accessed via the
12-bit parallel port. The parallel interface is selected holding the
SOE pin high. Data is transferred from the velocity and position
integrators, respectively, to the position and velocity registers
following a high-to-low transition on the SAMPLE pin. The
RDVEL polarity pin selects which register from the position or
the velocity registers is transferred to the output register. The CS
pin must be held low to transfer the selected data register to the
output register. Finally, the RD input is used to read the data
from the output register and to enable the output buffer. The
timing requirements for the read cycle are shown in Figure 7.
SAMPLE Input
Data is transferred from the position and velocity integrators,
respectively, to the position and velocity registers following a
high-to-low transition on the SAMPLE signal. This pin must be
held low for at least t1 ns to guarantee correct latching of the
data. RD should not be pulled low before this time since data
would not be ready. The converter will continue to operate
during the read process. Also, a rising edge of SAMPLE resets
the internal registers that contain the minimum and maximum
magnitude of the monitor signal.
CS Input
The device will be enabled when CS is held low.
RDVEL Input
RDVEL input is used to select between the angular position and
velocity registers as shown in Figure 7. RDVEL is held high for
angular position and low for angular velocity. The RDVEL pin
must be set (stable) at least t4 ns before the RD pin is pulled low.
RD Input
The 12-bit data bus lines are normally in a high impedance
state. The output buffer is enabled when CS and RD are held
low. A falling edge of the RD signal transfers data to the output
buffer. The selected data is made available to the bus to be read
within t6 ns of the RD pin going low. The data pins will return to
high impedance state when the RD returns to high state, within
t7 ns. If the user is reading data continuously, RD can be
reapplied a minimum of t5 ns after it was released.
Rev. 0 | Page 12 of 24

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