Datenblatt-pdf.com

AD2S105 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD2S105
Beschreibung Three-Phase Current Conditioner
Hersteller Analog Devices
Logo Analog Devices Logo 



Gesamt 12 Seiten
AD2S105 Datasheet, Funktion
a
FEATURES
Current Conditioning
Complete Vector Transformation on Silicon
Three-Phase 120° and Orthogonal 90° Signal
Transformation
Three-Phase Balance Diagnostic–Homopolar Output
DQ Manipulation
Real-Time Filtering
APPLICATIONS
AC Induction Motor Control
Spindle Drive Control
Pump Drive Control
Compressor Drive Control and Diagnostics
Harmonic Measurement
Frequency Analysis
Three-Phase Power Measurement
Three-Phase
Current Conditioner
AD2S105
FUNCTIONAL BLOCK DIAGRAM
Cosθ Sinθ
INPUT
DATA
STROBE
φ POSITION
PARALLEL
DATA
12 BITS
IS1
Cosθ
Cos (θ + 120°) IS2
IS3
Cos (θ + 240°)
Sinθ
Vds
SECTOR
MULTIPLIER
SINE AND
COSINE
MULTIPLIER
3φ-2φ
Vqs
SECTOR
MULTIPLIER
SINE AND
COSINE
MULTIPLIER
Vds'
Vqs'
BUSY
Cos θ + φ
Sin θ + φ
CONV1
CONV2
DECODE
Ia + Ib + Ic
3
HOMOPOLAR HOMOPOLAR +5V GND –5V
OUTPUT
REFERENCE
GENERAL DESCRIPTION
The AD2S105 performs the vector rotation of three-phase 120
degree or two-phase 90 degree sine and cosine signals by trans-
ferring these inputs into a new reference frame which is controlled
by the digital input angle φ. Two transforms are included in the
AD2S105. The first is the Clarke transform which computes
the sine and cosine orthogonal components of a three-phase in-
put. These signals represent real and imaginary components
which then form the input to the Park transform. The Park
transform relates the angle of the input signals to a reference
frame controlled by the digital input port. The digital input
port on the AD2S105 is a 12-bit/parallel natural binary port.
If the input signals are represented by Vds and Vqs, respectively,
where Vds and Vqs are the real and imaginary components, then
the transformation can be described as follows:
Vds' = Vds Cosφ – Vqs Sinφ
Vqs' = Vds Sinφ + Vqs Cosφ
Where Vds' and Vqs' are the output of the Park transform
and Sinφ, and Cosφ are the trigonometric values internally cal-
culated by the AD2S105 from the binary digital data φ.
The input section of the device can be configured to accept
either three-phase inputs, two-phase inputs of a three-phase
system, or two 90 degree input signals. The homopolar output
indicates an imbalance of a three-phase input only at a user-
specified level.
The digital input section will accept a resolution of up to 12 bits.
An input data strobe signal is required to synchronize the position
data and load this information into the device counters.
A two-phase rotated output facilitates the implementation of
multiple rotation blocks.
The AD2S105 is fabricated on LC2MOS and operates on
± 5 volt power supplies.
PRODUCT HIGHLIGHTS
Current Conditioning
The AD2S105 transforms the analog stator current signals (Is1,
Is2, Is3) using the digital angular signal (reference frame) into dc
values which represent direct current (Ids) and quadrature cur-
rent (Iqs). This transformation of the ac signals into dc values
simplifies the design of the analog-to-digital (A/D) conversion
scheme. The A/D conversion scheme is simplified as the band-
width sampling issues inherent in ac signal processing are
avoided and in most drive designs, simultaneous sampling of the
stator currents may not be necessary.
Hardware Peripheral for Standard Microcontroller and DSP
Systems
The AD2S105 off-loads the time consuming Cartesian transfor-
mations from digital processors and benchmarks show a signifi-
cant speed improvement over single processor designs. AD2S105
transformation time = 2 µs.
Field Oriented Control of AC Motors
The AD2S105 accommodates all the necessary functions to pro-
vide a hardware solution for current conditioning in variable
speed control of ac synchronous and asynchronous motors.
Three-Phase Imbalance Detection
The AD2S105 can be used to sense imbalances in a three-phase
system via the homopolar output.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD2S105 Datasheet, Funktion
AD2S105
CONVERTER OPERATION
The architecture of the AD2S105 is illustrated in Figure 3. The
AD2S105 is configured in the forward transformation which ro-
tates the stator coordinates to the rotor reference frame.
Vector Rotation
Position data, , is loaded into the input latch on the positive
edge of the strobe pulse. (For detail on the timing, please refer
to the “timing diagram.”) The negative edge of the strobe signi-
fies that conversion has commenced. A busy pulse is subse-
quently produced as data is passed from the input latches to the
Sin and Cos multipliers. During the loading of the multiplier,
the busy pulse remains high preventing further updates of in
both the Sin and Cos registers.
The negative edge of the busy pulse signifies that the multipliers
are set up and the orthogonal analog inputs are then multiplied
real time. The resultant two outputs are accessed via the
PH/OP1 (Pin 7) and PH/OP4 (Pin 6).
For other configurations, please refer to “Transformation
Configuration.”
CONNECTING THE CONVERTER
Power Supply Connection
The power supply voltages connected to VDD and VSS pins
should be +5 V dc and –5 V dc and must not be reversed. Pin 4
(VDD) and Pin 41 (VDD) should both be connected to +5 V;
similarly, Pin 5 (VSS) and Pin 19 (VSS) should both be con-
nected to –5 V dc.
It is recommended that decoupling capacitors, 100 nF (ceramic)
and 10 µF (tantalum) or other high quality capacitors, are con-
nected in parallel between the power line VDD, VSS and AGND
adjacent to the converter. Separate decoupling capacitors should
be used for each converter. The connections are shown in Fig-
ure 4.
+5V
+ 100nF
10µF
GND
10µF
+
100nF
1
AGND
12
AD2S105
TOP VIEW
34
23
–5V
Figure 4. AD2S105 Power Supply Connection
ANALOG SIGNAL INPUT AND OUTPUT CONNECTIONS
Input Analog Signals
All analog signal inputs to AD2S105 are voltages. There are two
different voltage levels of three-phase (0°, 120°, 240°) signal in-
puts. One is the nominal level, which is ± 2.8 V dc or 2 V rms
and the corresponding input pins are PH/IP1 (Pin 17), PH/IP2
(Pin 15), PH/IP3 (Pin 13) and PH/IP4 (Pin 11).
The high level inputs can accommodate voltages from nominal
up to a maximum of ± VDD/VSS. The corresponding input pins
are PH/IPH1 (Pin 16), PH/IPH2 (Pin 14) and PH/IPH3 (Pin
12). The homopolar output can only be used in the three-phase
connection mode.
The converter can accept both two-phase format and three-
phase format input signals. For the two-phase format input, the
two inputs must be orthogonal to each other. For the three-
phase format input, there is the choice of using all three inputs
or using two of the three inputs. In the latter case, the third in-
put signal will be generated internally by using the information
of other two inputs. The high level input mode, however, can
only be selected with three-phase/three-input format. All these
different conversion modes, including nominal/high input level
and two/three-phase input format can be selected using two se-
lect pins (Pin 23, Pin 24). The functions are summarized in
Table I.
Table I. Conversion Mode Selection
Mode Description
CONV1 CONV2
(Pin 23) (Pin 24)
MODE1
MODE2
MODE3
2-Phase Orthogonal with 2 Inputs
Nominal Input Level
3-Phase (0°, 120°, 240°) with 3 Inputs
Nominal/High Input Level*
3-Phase (0°, 120°, 240°) with 2 Inputs
Nominal Input Level
NC
DGND
VDD
DGND
VDD
VDD
*The high level input mode can only be selected with MODE2.
MODE1: 2-Phase/2 Inputs with Nominal Input Level
In this mode, PH/IP1 and PH/IP4 are the inputs and the Pins
12 through 16 must be left unconnected.
MODE2: 3-Phase/3 Inputs with Nominal/High Input Level
In this mode, either nominal or high level inputs can be used.
For nominal level input operation, PH/IP1, PH/IP2 and PH/IP3
are the inputs, and there should be no connections to PH/IPH1,
PH/IPH2 and PH/IPH3; similarly, for high level input opera-
tion, the PH/IPH1, PH/IPH2 and PH/IPH3 are the inputs, and
there should be no connections to PH/IP1, PH/IP2 and PH/IP3.
In both cases, the PH/IP4 should be left unconnected. For high
level signal input operation, select MODE2 only.
MODE3: 3-Phase/2 Inputs with Nominal Input Level
In this mode, PH/IP2 and PH/IP3 are the inputs and the third
signal will be generated internally by using the information of
other two inputs. It is recommended that PH/IP1, PH/IPH1,
PH/IPH2, PH/IP4 and PH/IPH3 should be left unconnected.
–6– REV. 0

6 Page









AD2S105 pdf, datenblatt
–12–

12 Page





SeitenGesamt 12 Seiten
PDF Download[ AD2S105 Schematic.PDF ]


Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD2S100AC Vector ProcessorAnalog Devices
Analog Devices
AD2S105Three-Phase Current ConditionerAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com    |   2020   |  Kontakt  |   Suche