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AD28MSP01 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD28MSP01
Beschreibung PSTN Signal Port
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 28 Seiten
AD28MSP01 Datasheet, Funktion
a
PSTN Signal Port
AD28msp01
FEATURES
Complete Analog l/O Port for DSP-Based FAX/MODEM
Applications
Linear-Coded 16-Bit Sigma-Delta ADC
Linear-Coded 16-Bit Sigma-Delta DAC
On-Chip Anti-Alias and Anti-lmage Filters
Digital Resampling/lnterpolation Filter
7.2 kHz, 8.0 kHz, and 9.6 kHz Sampling Rates
8/7 Mode for 8.23 kHz, 9.14 kHz, and 10.97 kHz
Sampling Rates
Synchronous and Asynchronous DAC/ADC Modes
Bit and Baud Clock Generation
Transmit Digital Phase-Locked Loop for Terminal
Synchronization
Independent Transmit and Receive Phase Adjustment
Serial Interface to DSP Processors
+5 V Operation with Power-Down Mode
28-Pin Plastic DlP/44-Lead PLCC/28-Lead SOIC
APPLICATIONS
High Performance DSP-Based Modems
V.32ter, V.32bis, V.32, V.22bis, V.22, V.21,
Bell 212A, 103
Fax and Cellular-Compatible Modems
V.33, V.29, V.27ter, V.27bis, V.27, V.26bis
Integrated Fax, Modem, and Speech Processing
FUNCTIONAL BLOCK DIAGRAM
ANALOG
INPUTS
16-BIT
SIGMA-DELTA
ADC
VOLTAGE
REFERENCE
RESAMPLING
INTERPOLATION
FILTER
SERIAL
PORT
DIGITAL
DATA AND
CONTROL
DIFFERENTIAL
ANALOG
OUTPUT
16-BIT
SIGMA-DELTA
DAC
CLOCK INPUTS
CLOCK OUTPUTS
CLOCK
GENERATION
GENERAL DESCRIPTION
The AD28msp01 is a complete analog front end for high perfor-
mance DSP-based modems. The device includes all data conver-
sion, filtering, and clock generation circuitry needed to imple-
ment an echo-cancelling modem with a single host digital signal
processor. Software-programmable sample rates and clocking
modes support all established modem standards. The AD28msp01
simplifies overall system design by requiring only +5 volts.
The inclusion of on-chip anti-aliasing and anti-imaging filters
and 16-bit sigma-delta ADC and DAC ensures a highly inte-
grated and compact solution for FAX or data MODEM applica-
tions. Sigma-delta conversion technology eliminates the need for
complex off-chip anti-aliasing filters and sample-and-hold circuitry.
The AD28msp01 utilizes advanced sigma-delta technology to
move the entire echo-cancelling modem implementation into the
digital domain. The device maintains a –72 dB SNR throughout
all filtering and data conversion. Purely DSP-based echo cancel-
lation algorithms can thereby maintain robust bit error rates
under worst-case signal attenuation and echo amplitude condi-
tions. The AD28msp01’s on-chip interpolation filter resamples
the received signal after echo cancellation in the DSP, freeing
the processor for other voice or data communications tasks.
On-chip bit and baud clock generation circuitry provides for
either synchronous or asynchronous operation of the transmit
(DAC) and receive (ADC) paths. Each path features indepen-
dent phase advance and retard adjustments via software control.
The AD28msp01 can also synchronize modem operation to an
external terminal bit clock.
The AD28msp01’s serial I/O port provides an easy interface to
host DSP microprocessors such as the ADSP-2101, ADSP-2105,
and ADSP-2111. Packaged in a 28-pin plastic DIP, 44-lead
PLCC, 44-pin TQFP, or 28-lead SOIC, the AD28msp01 pro-
vides a compact solution for space-constrained environments.
The device operates from a +5 V supply and offers a low power
sleep mode for battery-powered systems.
A detailed block diagram of the AD28msp01 is shown in
Figure 1.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD28MSP01 Datasheet, Funktion
AD28msp01
goodstuff;
.ENDMOD;
AX0 = DM(I2, M1);
AY0 = 8;
AR = AX1 – AY0;
IF EQ JUMP goodstuff;
RTI;
MODIFY (I3, M1);
DM(I3, M0) = AX0;
MX1 = 6;
AR = 0x06a7;
DM(0x3ff3) = AR;
TX0 = MX1;
RTI;
{Read data word}
{Verify AD28msp01 address = 8}
{Point to second word of TX buffer}
{Load address word into MX1}
{Enable TX and RX autobuffer}
{Write to SPORT control Register}
{Autobuffer start}
Figure 4. AD28msp01 Initialization and ADSP-2101 Loopback Routine
Serial Data Output
When the digital power-down bit (PWDD) of Control Register 1
is set to 1, the AD28msp01’s SPORT begins transmitting data to
the host processor. All transfers between the host processor and
the AD28msp01 consist of a serial data output frame sync
(SDOFS) followed by a 16-bit address word, then a second
frame sync followed by a 16-bit data word. Address/data word
pairs are transmitted whenever they become available. The
ADC takes precedence over the Interpolator output data. If a
new word becomes available while a serial transfer is in progress,
the current serial transfer is completed before the new word starts
transmission.
Serial Data Input
The host processor must initiate data transfers to the
AD28msp01 by asserting the serial data input frame sync
(SDIFS) high. Each of the 16-bit address word and 16-bit data
word transfers begins one serial clock cycle after SDIFS is as-
serted. The address word always precedes the data word. The
second serial data input frame sync for the data word can be as-
serted as early as the last bit of the address word is transmitted,
or any time after.
The host processor must assert SDIFS shortly after the rising
edge of SCLK and must maintain SDIFS high for one cycle be-
cause SDIFS is clocked by the SCLK falling edge. Data is then
driven from the host processor shortly after the rising edge of
the next SCLK and is clocked into the AD28msp01 on the fall-
ing edge of SCLK in that cycle. Each bit of a 16-bit address and
16-bit data word is thus clocked into the AD28msp01 on the
falling edge of SCLK (MSB first).
and receive timing as well as an additional clock signal for serial
port timing.
The receive clocks are the RCONV, RBIT and RBAUD signals.
The individual clock rates are programmable and are all syn-
chronized with RCONV.
The transmit clocks are the TCONV, TBIT and TBAUD sig-
nals. The individual clock rates are programmable and are all
synchronized with TCONV.
Depending on the operating mode, the converter clocks can be
synchronized to an external clock signal (TSYNC) or can be
generated internally. The clocks can be adjusted in phase by set-
ting the appropriate phase adjust register. All the AD28msp01
Bit/Baud clocks have a 50% duty cycle except the 1600 Hz baud
rate. This baud rate has a 33%–66% duty cycle.
Resampling Interpolation Filter
The resampling interpolation filter interpolates the data from
the TCONV rate to 1.7280 MHz. The data is then resampled
(decimated) in phase with the RCONV clock. The frequency re-
sponse characteristics of the resampling interpolation filter are
identical to the frequency response characteristics of the anti-
imaging, low-pass filter/interpolation filter combination.
Figure 5 illustrates the effects of a resampling interpolation
filter.
ANALOG SIGNAL
SAMPLED AT 9600 Hz
If SDIFS is asserted high again before the end of the present
data word transfer, it is not recognized until the falling edge of
SCLK in the last (LSB) cycle.
OUTPUT OF
INTERPOLATION
FILTER
When the serial port receives an interpolator or DAC input
word, it writes the value to an internal register which is read by
the AD28msp01 when it is needed. This allows the host to send
data words at any time during the sample period.
OUTPUT OF
RESAMPLING
FILTER
NOTE: Exact SPORT timing requirements are defined in the
“Specifications” section of this data sheet.
Clock Generation
The AD28msp01 generates all transmit and receive clocks
necessary to implement standard voice-grade modems. The
AD28msp01 can generate six different clock signals for transmit
Figure 5. Effects of Interpolation Filter
–6– REV. A

6 Page









AD28MSP01 pdf, datenblatt
AD28msp01
V.32 Internal Sync Mode
In V.32 Internal Sync Mode, shown in Figure 8, the AD28msp01’s
transmit clocks are generated internally. The receive circuitry
operates synchronous to the transmit circuitry, but the data can
be resampled at a different phase through the resampling inter-
polation filter.
TCONV, TBIT and TBAUD are generated internally and can
be phase adjusted with the Transmit Phase Adjust Register
(Control Register 5). RCONV, RBIT and RBAUD are also gen-
erated internally and can be phase adjusted with the Receive
Phase Adjust Register (Control Register 4).
TCONV initiates a new ADC sample update, loads the ADC
register (Data Register 2), and loads the DAC register (Data
Register 0) with a new sample.
The digital resampling interpolation filter can be used for digital
resampling of the received signal. Enable this function by setting
Bit 9 in Control Register 0. The phase of the resampled signal is
adjusted with the Receive Phase Adjust Register. Samples are
loaded into the interpolator at the TCONV rate and are
resampled at the RCONV rate.
When entering V.32 Internal Sync Mode, RCONV is first
locked to TCONV. RCONV is then phase adjusted whenever a
new value is written to the Receive Phase Adjust Register (Con-
trol Register 4). If this mode is entered from a non-V.32 mode,
the device performs a soft reset. The time required to lock
TCONV to RCONV is dependent on the phase difference be-
tween RCONV and TCONV when entering the mode.
This mode is entered by setting the Operating Mode field in
Control Register 0. The RCONV/TCONV rate can be set to
9.6 kHz, 8.0 kHz or 7.2 kHz by setting the sample rate bit field
in Control Register 0. The TBIT and TBAUD clock rates are
set by adjusting the appropriate bits in Control Register 3. The
RBIT and RBAUD clock rates are set by adjusting the appropri-
ate bits in Control Register 2. The bit and baud rates can be set
to any combination of clock rates listed in the control register
descriptions.
ANALOG IN
MCLK
ANALOG OUT
16
A/D
DATA
REGISTER 2
TX CLOCKS
TCONV
TBIT
TBAUD
PHASE ADJUST
CONVERT
START
CONTROL
REGISTER 5
TX PHASE ADJUST
AD28msp01
16
RXRCXLCOLCOKCSKS
RCONV
RBIT
RBAUD
PHASE ADJUST
CONTROL
REGISTER 4
RX PHASE ADJUST
INTERPOLATION
FILTER
DATA
REGISTER 1
16
PHASE
ADJUST
16
DATA
REGISTER 3
16
D/A
DATA
REGISTER 0
16
DSP Processor
16 ECHO
CANCELLATION
16
TO MODEM RX
FROM MODEM TX
Figure 8. V.32 Internal Sync Mode Block Diagram
–12–
REV. A

12 Page





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