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AD20MSP410 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD20MSP410
Beschreibung GSM Baseband Processing Chipset
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 8 Seiten
AD20MSP410 Datasheet, Funktion
a
GSM
Baseband Processing Chipset
FEATURES
Passed European GSM Phase I Type Approval
Complete Baseband Processing Chipset Performs:
Speech Coding/Decoding, According to GSM 06.XX
DTMF and Call Progress Tone Generation
Equalization with 16-State Viterbi, Soft Decision
Channel Coding/Decoding According to GSM 05.03
All ADC and DAC Interface Functions
Includes all Radio, Auxiliary and Voice Interfaces
Support for GSM Data Services
Embedded 16-Bit Microcontroller
Layer 1 Software Provided with Chipset
Full Phase 2 Protocol Stack Software Available
Integrated SIM- and Keyboard Interface
Ultralow Power Design
2.7 V Operating Voltage
Intelligent Power Management Features
Up to 70 Hours Standby Time Achievable
JTAG-Boundary Scan
Full Reference Design Available
Three TQFP Devices, Occupying Less than 12 cm2
APPLICATIONS
GSM/DCS1800 Mobile Radios and PCMCIA Cards
AD20msp410
SYSTEM ARCHITECTURE
ALGORITHM
SIGNAL
PROCESSOR
ASP
PHYSICAL
LAYER
PROCESSOR
AD20msp410
GSM CHIPSET
PLP
µC
BASEBAND
CONVERTER
BBC
RADIO
SUBSYSTEM
512K x 16 128K x 8
ROM
RAM
DISPLAY
2K x 8
EEPROM
KEYPAD
SIM
GENERAL DESCRIPTION
The Analog Devices GSM baseband processing chipset provides
a competitive solution for GSM based mobile radio systems. It
is designed to be fully integrated, easy to use, and compatible
with a wide range of product solutions. GSM phones using this
chipset and its accompanying Layer 1, 2, 3 software have passed
the European GSM full type approval process.
The chipset consists of three highly integrated, sub-micron, low
power CMOS components that form the core baseband signal
processing of the GSM handset. The system architecture is
designed to be easily integrated into current designs and form
the basis of next generation of designs.
The chipset uses an operating voltage of 2.7 V to 3.6 V, which
coupled with the extensive power management features,
significantly reduces the drain on battery power and extends the
handset’s talktime and standby time.
CHIPSET COMPONENTS
Algorithm Signal Processor (ASP)
The ASP is an application specific variant of the ADSP-2171
standard DSP from Analog Devices. It has been optimized to
meet the cost, size and power consumption requirements of
GSM mobile applications. All necessary memory to run the
GSM specific programs is provided on-chip and with its
preprogrammed ROM, no user programming is required. The
ASP implements full rate speech transcoding according to GSM
specifications, including Discontinuous Transmission (DTX)
and Comfort Noise Insertion (CNI). A high performance soft-
decision Viterbi equalizer is also implemented in software,
embedded in the ROM.
Physical Layer Processor (PLP)
The PLP combines application specific hardware and an
embedded 16-bit microcontroller (Hitachi H8/300H) to
perform channel coding and decoding and execute the protocol
stack and user software. The embedded processor executes the
Layer 1, 2, 3 and user MMI software. The PLP can control all
powerdown functions of the other chips and memory support
components to achieve maximum power savings.
Baseband Converter (BBC)
The BBC performs the voiceband and baseband analog-to-
digital and digital-to-analog conversions, interfacing the digital
sections of the chipset to the microphone, loudspeaker and radio
section. In addition, the BBC contains all the auxiliary convert-
ers for burst-ramping, AFC, AGC, battery and temperature
monitoring. The chipset interfaces directly with a variety of
industry standard radio architectures and supplies all the
synthesizer and timing control signals.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD20MSP410 Datasheet, Funktion
AD20msp410
Digital Audio Interface (DAI)
As required by the GSM specifications, a digital audio interface
is provided to allow certain tests of the audio section during type
approval. This interface is provided by the serial bus between
the ASP and the PLP and two additional control signals from
the PLP. A fully functional “DAI Box” needed for the FTA
process may be obtained from Analog Devices upon request.
Digital Interface to the PLP for Data Services
A conventional H8 serial port combined with a proprietary
protocol is used to interface to an external Data Terminal
Adapter.
Digital Interface from the PLP to the EEPROM
The PLP provides separate pins to interface directly to an
external EEPROM via a serial port. This EEPROM is typically
used for storage of calibration or user variable parameters like
handset identifier (IMEI), language, keypad lock and radio
calibration parameters. A typical size of the EEPROM is 2K × 8
bits, but this depends on the individual design of the handset.
GSM Baseband Processing Key Parts List
Table 1 lists the major hardware components necessary to
complete the GSM baseband processing subsystem. An example
Bill Of Material is available from Analog Devices. A full
reference design is available through Analog Devices/The
Technology Partnership.
Table I. List of Key Components
Quantity
1
1
1
1
1
1
1
Description
ASP1
PLP1
BBC1
FLASH-PROM2
SRAM
EEPROM3
Display Driver
Specification
ADSP-2178
ADPLP01
AD7015
256K × 16, 150 ns
128K × 8, 120 ns
2K × 8
Design Specific
NOTES
1These components comprise the AD20msp410 chipset.
2A size of 4 Mbits is recommended to allow storage of all GSM Layer
(1, 2, 3) programs as well as a typical user interface (MMI). Larger
memory can be used to support enhanced user interfaces.
3Can be omitted if parameters are stored in FLASH memory.
KEYPAD
KEYPAD
DATA
INTERFACE
PLP
SIM
INTERFACE
SERIAL PORT DAI CONTROL
ADDRESS
DATA
PSRAM
CONTROL
ASP
INTERFACE
DISPLAY
CONTROL
BACKLIGHT
CONTROL
KEYPAD
INTERFACE
EEPROM
INTERFACE
DATA
INTERFACE
POWER
CONTROL
SYNTHESIZER
AND RADIO
CONTROL
13MHz
VCTCXO
DAI
INTERFACE
SPORT 0
ASP
ADDRESS
DATA BUS
SPORT 1
CLOCK
POWER
SUBSYSTEM
BBC
AUX DAC 2
(AFC)
VOICEBAND
ANALOG I/O
VOICEBAND
SERIAL PORT
AUX DAC 1
(AGC)
BASEBAND
SERIAL PORT
AUX DAC 3
(AGC)
BASEBAND
ANALOG I/O
AUX ADC
Figure 5. System Interfaces
CAR KIT
POWER
AMPLIFIER
RADIO
IF
AMPLIFIER
MODULATOR
DEMODULATOR
SYNTHESIZER
AND RADIO
CONTROL
–6– REV. 0

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