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PDF AD10265 Data sheet ( Hoja de datos )
| Número de pieza | AD10265 | |
| Descripción | 65 MSPS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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aDual Channel, 12-Bit, 65 MSPS A/D Converter
with Analog Input Signal Conditioning
AD10265
FEATURES
Dual, 65 MSPS Minimum Sample Rate
Channel-Channel Matching, ؎0.1% Gain Error
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Selectable Bipolar Input Voltage Range
(؎0.5 V, ؎1.0 V, ؎2.0 V)
Gain Flatness up to Nyquist: < 0.5 dB
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
1.05 W Per Channel
Industrial and Military Grade
APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Anti-Jamming Receivers
Multichannel, Multimode Receivers
PRODUCT DESCRIPTION
The AD10265 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
includes two wide dynamic range AD6640 ADCs. Each AD6640
has an AD9631/AD9632 ac-coupled amplifier front end. The
AD6640s have on-chip track-and-hold circuitry, and utilize an
innovative multipass architecture, to achieve 12-bit, 65 MSPS
performance. The AD10265 uses innovative high-density
circuit design and laser-trimmed thin-film resistor networks to
achieve exceptional matching and performance while still main-
taining excellent isolation, and providing for significant board
area savings.
The AD10265 operates with ± 5.0 V for the analog signal
conditioning with a separate +3.3 V supply for the analog-to-
digital conversion. Each channel is completely independent
allowing operation with independent Encode and Analog
inputs. The AD10265 also offers the user a choice of Analog
Input Signal ranges to further minimize additional external
signal conditioning, while still remaining general-purpose.
The AD10265 is packaged in a 68-lead ceramic gull wing pack-
age, footprint compatible with the earlier generation AD10242
(12-bit, 40 MSPS). Manufacturing is done on Analog Devices’
MIL-38534 Qualified Manufacturers Line (QML) and com-
ponents are available up to Class-T (–25°C to +125°C). The
AD6640 internal components are manufactured on Analog
Devices’ high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input amplitude options, user configurable.
3. Input signal conditioning included; both channels matched
for gain.
4. Fully tested/characterized performance for full channel.
5. Footprint compatible family; 68-lead LCCC.
AINA3
FUNCTIONAL BLOCK DIAGRAM
AINA2
AINA1
AINB3
AINB2
AINB1
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
AD9632
AD9631
AD9632
AD9631
9
TIMING
AIN AIN
AD6640
12
OUTPUT BUFFERING
AD10265
AIN AIN
AD6640
12
OUTPUT BUFFERING
7
TIMING
5
ENCODEB
ENCODEB
D11B (MSB)
D10B
D9B
D8B
D7B
ENCODEA ENCODEA D9A D10A D11A
(MSB)
D0B D1B D2B D3B D4B D5B D6B
(LSB)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
Pin No.
1
2, 5, 9–11, 26, 27
3, 4, 12, 15, 16,
34, 35, 55–57
6
7
8
13
14
17–25, 31–33
28
29
30
36–42, 45–49
43, 44, 53, 54,
58–61, 65, 68
50
51
52
62
63
64
66
67
AD10265
Name
SHIELD
GNDA
NC
AINA1
AINA2
AINA3
AVEE
AVCC
D0A–D11A
ENCODEA
ENCODEA
DVCC
D0B–D11B
GNDB
DVCC
ENCODEB
ENCODEB
AINB1
AINB2
AINB3
AVCC
AVEE
PIN FUNCTION DESCRIPTIONS
Function
Internal Ground Shield between channels.
A Channel Ground. A and B grounds should be connected as close to the device as possible.
No Connect. Pins 15 and 16 are internal test pins: it is recommended to connect
them to GND.
Analog Input for A side ADC (nominally ± 0.5 V).
Analog Input for A side ADC (nominally ± 1.0 V).
Analog Input for A side ADC (nominally ± 2.0 V).
Analog Negative Supply Voltage (nominally –5.0 V). For A side ADC.
Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC.
Digital Outputs for ADC A. D0 (LSB).
ENCODE is complement of ENCODE.
Data conversion initiated on rising edge of ENCODE input.
Digital positive supply voltage (nominally 3.3 V) for A side ADC.
Digital Outputs for ADC B. D0 (LSB).
B Channel Ground. A and B grounds should be connected as close to the device
as possible.
Digital Positive Supply Voltage (nominally 3.3 V) for B side ADC.
Data conversion initiated on rising edge of ENCODE input.
ENCODE is complement of ENCODE.
Analog Input for B side ADC (nominally ± 0.5 V).
Analog Input for B side ADC (nominally ± 1.0 V).
Analog Input for B side ADC (nominally ± 2.0 V).
Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC.
Analog Negative Supply Voltage (nominally –5.0 V). For B side ADC.
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
GNDA 10
GNDA 11
NC 12
AVEE 13
AVCC 14
NC 15
NC 16
(LSB) D0A 17
D1A 18
D2A 19
D3A 20
D4A 21
D5A 22
D6A 23
D7A 24
D8A 25
GNDA 26
PIN 1
AD10265
TOP VIEW
(Not to Scale)
60 GNDB
59 GNDB
58 GNDB
57 NC
56 NC
55 NC
54 GNDB
53 GNDB
52 ENCODEB
51 ENCODEB
50 DVCC
49 D11B (MSB)
48 D10B
47 D9B
46 D8B
45 D7B
44 GNDB
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC = NO CONNECT
REV. A
–5–
5 Page 
AD10265
If a low jitter ECL clock is available, another option is to ac-couple
a differential ECL signal to the encode input pins as shown
below. The capacitors shown here should be chip capacitors,
but do not need to be of the low inductance variety.
ECL
GATE
510⍀
0.1F
0.1F
510⍀
ENCODE
AD10265
ENCODE
–VS
Figure 11. Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
AD96687 (1/2)
50⍀
510⍀
0.1F
0.1F
510⍀
ENCODE
AD10265
ENCODE
–VS
Figure 12. ECL Comparator for Encode
USING THE FLEXIBLE INPUT
The AD10265 has been designed with the user’s ease of operation
in mind. Multiple input configurations have been included on
board to allow the user a choice of input signal levels and input
impedance. While the standard inputs are ±0.5 V, ±1.0 V, and
±2.0 V, the user can select the input impedance of the AD10265
on any input by using the other inputs as alternate locations for
GND or an external resistor. The following chart summarizes
the impedance options available at each input location:
AIN1 = 100 Ω when AIN2 and AIN3 Are Open.
AIN1 = 75 Ω when AIN3 Is Shorted to GND.
AIN1 = 50 Ω when AIN2 Is Shorted to GND.
AIN2 = 200 Ω when AIN3 Is Open.
AIN2 = 100 Ω when AIN3 Is Shorted to GND.
AIN2 = 75 Ω when AIN2 to AIN3 Has an External Resistor of
AIN2 = 300 Ω, with AIN 3 Shorted to GND.
AIN2 = 50 Ω when AIN2 to AIN3 Has an External Resistor of
AIN2 = 100 Ω, with AIN3 Shorted to GND.
AIN3 = 400 Ω.
AIN3 = 100 Ω when AIN3 Has an External Resistor of 133 Ω to GND.
AIN3 = 75 Ω when AIN3 Has an External Resistor of 92 Ω to GND.
AIN3 = 50 Ω when AIN3 Has an External Resistor of 57 Ω to GND.
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electromagnetic
interference (EMI) and an overall improvement in performance.
It is important to design a layout that prevents noise from coupling
to the input signal. Digital signals should not be run in parallel
with input signal traces and should be routed away from the
input circuitry. The AD10265 does not distinguish between
analog and digital ground pins as the AD10265 should always
be treated as an analog component. All ground pins should be
connected together directly under the AD10265. The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. The ground plane
should be removed from the area near the input pins to reduce
stray capacitance.
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 13) represents
a typical implementation of the AD10265. The pinout of the
AD10265 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the AD6640 ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
REV. A
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD10265.PDF ] | |
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