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PDF ACT3492 Data sheet ( Hoja de datos )
| Número de pieza | ACT3492 | |
| Descripción | MIL-STD-1553B Remote Terminal/ BUS Controller/ or Passive Monitor Hybrid with Status Word Control Dual Low Power Monolithic BUS Tranceivers | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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ACT3492 Series
MIL-STD-1553B Remote Terminal, BUS Controller,
or Passive Monitor Hybrid with Status Word Control
Dual Low Power Monolithic BUS Tranceivers
Features
• Dual Low Power Monolithic Bus Tranceivers
• Performs the Complete Dual-Redundant Remote Terminal, Bus Controller Protocol
and Passive Monitor Functions of MIL-STD-1553B
• Automated Self-Test Functions
• Allows Setting of the Message Error Bit on Illegal Commands
• Provides programmable control over Terminal Flag and Subsystem Flag Status Bits
• MIL-PRF-38534 Compliant Circuits Available
• 250 mw Typical Power Consumption
• Small Size
• Available in Ceramic Plug-in Package Configuration
• 5V DC Operation
• Full Military (-55°C to +125°C) Temperature Range
CIRCUIT TECHNOLOGY
www.aeroflex.com
• DESC SMD# Pending
1
General Description
The ACT3492 Series is a monolithic implementation of the MIL-STD-1553B Bus Controller, Remote
Terminal and Passive Monitor functions including dual low power Bus tranceivers. All protocol functions
of MIL-STD-1553B are incorporated and a number of options are included to improve flexibility. These
features include programming of the status word, illegalizing specific commands and an independent loop
back self-test which is initiated by the subsystem. This unit is directly compatible with all microprocessor
interfaces such as the CT1611 and CT1800 produced by Aeroflex Incorporated.
Block Diagram (With Transformers)
Encoder
Interface
Unit
Sub Address
&
Word Count
Outputs
BUS "0"
BUS "1"
ASIC
T/R
Hybrid
ASIC
T/R
Hybrid
Driver
Select
&
Enable
Decoder
"O"
Decoder
"1"
Status
Word
Control
Internal
Highway
Control
Program
Inputs
Discrete
Outputs
Control
Inputs
Terminal
Address
Inputs
ASIC
ACT3492
eroflex Circuit Technology – Data Bus Modules For The Future © SCD3492 REV B 6/26/01
1 page  
REMOTE TERMINAL OPERATION
Receive Data Operation
All valid data words associated with a valid receive data command word for the RT are passed to the
subsystem. The RT examines all command words from the bus and will respond to valid (i.e. correct
Manchester, parity coding etc.) commands which have the correct RT address (or broadcast address if the
RT broadcast option is enabled). When the data words are received, they are decoded and checked by the
RT and, if valid, passed to the subsystem on a word by word basis at 20 µs intervals. This applies to receive
data words in both Bus Controller to RT and RT to RT messages. When the RT detects that the message
has finished, it checks that the correct number of words have been received and if the message is fully valid,
then a Good Block Received signal is sent to the subsystem, which must be used by the subsystem as
permission to use the data just received.
The subsystem must therefore have a temporary buffer store up to 32 words long into which these data
words can be placed. The Good Block Received signal will allow use of the buffer store data once the
message has been validated.
If a block of data is not validated, then Good Block Received will not be generated. This may be caused by
any sort of message error or by a new valid command for the RT being received on another bus to which the
RT must switch.
Transmit Data Operation
If the RT receives a valid transmit data command addressed to the RT, then the RT will request the data
words from the subsystem for transmission on a word by word basis. To allow maximum time for the
subsystem to collect each data word, the next word is requested by the RT as soon as the transmission of
the current word has commenced.
It is essential that the subsystem should provide all the data words requested by the RT once a transmit
sequence has been accepted. Failure to do so will be classed by the RT as a subsystem failure and
reported as such to the Bus Controller.
Control of Data Transfers
This section describes the detailed operation of the data transfer mechanism between the RT and
subsystems. It covers the operations of the signals DTRQ, DTAK, IUSTB, H/L, GBR, NBGT, TX/RX during
receive data and transmit data transfers. Figures 29 and 30 show typical interfacing logic.
Figures 5 and 15 shows the operation of the data handshaking signals during a receive command with one
data word. When the RT has fully checked the command word, NBGT is pulsed low, which can be used by
the subsystem as an initialization signal. TX/RX will be set low indicating a receive command. When the first
data word has been fully validated, DTRQ is set low. The subsystem must then reply within approximately
1.5 µs by setting DTAK low. This indicates to the RT that the subsystem is ready to accept data. The data
word is then passed to the subsystem on the internal highway IH08-IH715 in two bytes using IUSTB as a
strobe signal and H/L as the byte indicator (high byte first followed by low byte). Data is valid about both
edges of IUSTB. Signal timing for this handshaking is shown in Figure 15. Also see Figures 19 and 20.
If the subsystem does not declare itself busy, then it must respond to DTRQ going low by setting DTAK low
within approximately 1.5 us. Failure to do so will be classed by the RT as a subsystem failure and reported
as such to the Bus Controller.
It should be noted that IUSTB is also used for internal working in the RT. DTRQ being low should be used as
an enable for clocking data to the subsystem with IUSTB.
Once the receive data block has finished and been checked by the RT, GBR is pulsed low if the block is
entirely correct and valid. This is used by the subsystem as permission to make use of the data block. If no
GBR signal is generated, then an error has been detected by the RT and the entire data block is invalid and
no data words in it may be used.
If the RT is receiving data in an RT to RT transfer, the data handshaking signals will operate in an identical
Aeroflex Circuit Technology
5 SCD3492 REV B 6/26/01 Plainview NY (516) 694-6700
5 Page 
fault coverage. The monolithic circuit includes all circuitry required to perform the self-test.
Self-test can be an on-line or off-line function which is initiated by simple subsystem intervention. The
DRVINH signal selects on-line or off-line testing. The circuit accomplishes the on-line test without
accessing the MIL-STD-1553 data bus by providing an internal data path which connects the encoder
circuitry directly to the decoder circuitry. The transceiver is inhibited during this on-line test. The off-line
test is designed to include the transceiver as well as the protocol device. This mode will generally be useful
as an off-line card test where no live bus is in use.
To initiate the self-test a word is placed in the Vector Word Latch, Loop Test Enable (LTEN) is held low, and
the Loop Test Trigger (LTTRIG) signal is pulsed low. The primary bus will be tested with the word that
resides in the Vector Word Latch, encoded then looped back, decoded and presented to the subsystem as
a normal data transfer would be accomplished. The secondary bus is sequentially tested after the primary
bus is completed via Request Bus A (REQBUSA) utilizing the same word residing in the Vector Word
Latch. Upon completion of each test, pass/fail signals will be asserted reporting the results of the test.
This test implementation verifies MIL-STD-1553 protocol compliance; proper sync character, 16 data bits,
Manchester II coding, odd parity, contiguous word checking and a bit by bit comparison of the transmitted
data. The self-test circuitry increases the fault coverage by insuring that the internal function blocks;
encoder, decoder, and internal control circuitry are operating correctly. An effective data pattern to
accomplish this is HEX AA55 since each bit is toggled, (8 bit internal highway) on a high/low byte basis.
The total time required to complete the self-test cycle is 89 microseconds. The Loop Test Enable signal
must remain in the low state throughout the diagnostic cycle.
Aeroflex Circuit Technology
11 SCD3492 REV B 6/26/01 Plainview NY (516) 694-6700
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ACT3492.PDF ] | |
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