PDF AD5232 Data sheet ( Hoja de datos )

Número de pieza	AD5232
Descripción	Dual 256-Position Digital Potentiometer
Fabricantes	Analog Devices
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Data Sheet Nonvolatile Memory, Dual 256-Position Digital Potentiometer AD5232 FEATURES Dual-channel, 256-position resolution 10 kΩ, 50 kΩ, and 100 kΩ nominal terminal resistance Nonvolatile memory maintenance of wiper settings Predefined linear increment/decrement instructions Predefined ±6 dB step log taper increment/decrement instructions SPI-compatible serial interface Wiper settings and EEMEM readback 3 V to 5 V single-supply operation ±2.5 V dual-supply operation 14 bytes of general-purpose user EEMEM Permanent memory write protection 100-year typical data retention (TA = 55°C) APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The AD5232 device provides a nonvolatile, dual-channel, digitally controlled variable resistor (VR) with 256-position resolution. This device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. The versatile programming of the AD5232, per- ormed via a microcontroller, allows multiple modes of operation and adjustment. In the direct program mode, a predetermined setting of the RDAC registers (RDAC1 and RDAC2) can be loaded directly from the microcontroller. Another important mode of operation allows the RDACx register to be refreshed with the setting previously stored in the corresponding EEMEM register (EEMEM1 and EEMEM2). When changes are made to the RDACx register to establish a new wiper position, the value of the setting can be saved into the EEMEMx register by executing an EEMEM save operation. After the settings are saved in the EEMEMx register, these values are automatically transferred to the RDACx register to set the wiper position at system power-on. Such operation is enabled by the internal preset strobe. The preset strobe can also be accessed externally. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. FUNCTIONAL BLOCK DIAGRAM VDD CS CLK SDI SDO ADDR DECODE SERIAL INTERFACE RDAC1 REGISTER EEMEM1 AD5232 RDAC1 A1 W1 B1 POWER-ON PR RESET WP RDY EEMEM CONTROL RDAC2 REGISTER EEMEM2 14 BYTES USER EEMEM RDAC2 A2 W2 B2 GND Figure 1. VSS All internal register contents can be read via the serial data output (SDO). This includes the RDAC1 and RDAC2 registers, the corresponding nonvolatile EEMEM1 and EEMEM2 registers, and the 14 spare USER EEMEM registers that are available for constant storage. The basic mode of adjustment is the increment and decrement command instructions that control the wiper position setting register (RDACx). An internal scratch pad RDACx register can be moved up or down one step of the nominal resistance between Terminal A and Terminal B. This step adjustment linearly changes the wiper to Terminal B resistance (RWB) by one position segment of the device’s end-to-end resistance (RAB). For exponential/ logarithmic changes in wiper setting, a left/right shift command instruction adjusts the levels in ±6 dB steps, which can be useful for audio and light alarm applications. The AD5232 is available in a thin, 16-lead TSSOP package. All parts are guaranteed to operate over the extended industrial temperature range of −40°C to +85°C. An evaluation board, the EVAL-AD5232-10EBZ, is available. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2001–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD5232 INTERFACE TIMING CHARACTERISTICS All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 5 V. Table 2. Parameter1, 2 Symbol Conditions Min Typ3 Max Unit Clock Cycle Time (tCYC) t1 20 ns CS Setup Time t2 10 ns CLK Shutdown Time to CS Rise t3 1 tCYC Input Clock Pulse Width t4, t5 Clock level high or low 10 ns Data Setup Time t6 From positive CLK transition 5 ns Data Hold Time t7 From positive CLK transition 5 ns CS to SDO-SPI Line Acquire t8 40 ns CS to SDO-SPI Line Release t9 50 ns CLK to SDO Propagation Delay4 t10 RP = 2.2 kΩ, CL < 20 pF 50 ns CLK to SDO Data Hold Time t11 RP = 2.2 kΩ, CL < 20 pF 0 ns CS High Pulse Width5 t12 10 ns CS High to CS High5 t13 4 tCYC RDY Rise to CS Fall t14 0 ns CS Rise to RDY Fall Time t15 0.15 0.3 ms Store/Read EEMEM Time6 t16 Applies to Command Instruction 2, Command 25 ms Instruction 3, and Command Instruction 9 CS Rise to Clock Rise/Fall Setup t17 10 ns Preset Pulse Width (Asynchronous) tPRW Not shown in timing diagram 50 ns Preset Response Time to RDY High tPRESP PR pulsed low to refresh wiper positions 70 µs 1 Guaranteed by design; not subject to production test. 2 See the Timing Diagrams section for the location of measured values. 3 Typicals represent average readings at 25°C and VDD = 5 V. 4 Propagation delay depends on the value of VDD, RPULL-UP, and CL. 5 Valid for commands that do not activate the RDY pin. 6 RDY pin low only for Command Instruction 2, Command Instruction 3, Command Instruction 8, Command Instruction 9, Command Instruction 10, and the PR hardware pulse: CMD_8 ~ 1 ms, CMD_9 = CMD_10 ~ 0.12 ms, and CMD_2 = CMD_3 ~ 20 ms. Device operation at TA = −40°C and VDD < 3 V extends the save time to 35 ms. Rev. C \| Page 5 of 24 5 Page Data Sheet 0 0x80 –6 0x40 –12 –18 –24 –30 –36 –42 –48 VDD = +2.7V –54 VSS = –2.7V VA = 100mV rms –60 TA = 25°C 1k 0x20 0x10 0x08 0x04 0x02 0x01 VA RAB = 10kΩ 10k 100k FREQUENCY (Hz) 1M Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ 0 0x80 –6 0x40 –12 0x20 –18 0x10 –24 –30 –36 –42 –48 VDD = +2.7V –54 VSS = –2.7V VA = 100mV rms –60 TA = 25°C 1k 0x08 0x04 0x02 0x01 VA RAB = 50kΩ 10k 100k FREQUENCY (Hz) 1M Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ 0 –6 0x80 –12 0x40 0x20 –18 0x10 –24 0x08 –30 0x04 –36 0x02 –42 –48 VDD = +2.7V –54 VSS = –2.7V VA = 100mV rms –60 TA = 25°C 1k 0x01 VA RAB = 100kΩ 10k 100k FREQUENCY (Hz) Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ 1M AD5232 80 RAB = 100kΩ RAB = 50kΩ 60 RAB = 10kΩ 40 VDD = 5.5V ± 100mV AC 20 VSS = 0V VB = 5V VA = 0V MEASURE AT VW WITH CODE = 0x80 TA = 25°C 0 1k 10k 100k FREQUENCY (Hz) Figure 20. PSRR vs. Frequency 120 1M 100 80 RAB = 10kΩ RAB = 100kΩ 60 RAB = 50kΩ 40 VDD = VA2 = +2.75V VSS = VB2 = –2.75V VIN = +5V P-P TA = 25°C 20 1 10 FREQUENCY (kHz) 100 Figure 21. Analog Crosstalk vs. Frequency (See Figure 31) Rev. C \| Page 11 of 24 11 Page

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