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AD7466 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7466
Beschreibung 1.8 V/ Micro-Power/ 8/10/12-Bit ADCs in 6 Lead SOT-23
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 15 Seiten
AD7466 Datasheet, Funktion
a
pecifications
1.8 V, Micro-Power,
8/10/12-Bit ADCs in 6 Lead SOT-23
Preliminary Technical Data
AD7466/AD7467/AD7468
FEATURES
Specified for VDD of 1.8 V to 3.6 V
Low Power:
0.9 mW max at 60 kSPS with 3.6 V Supplies
0.4 mW max at 100 kSPS with 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
Wide Input Bandwidth:
70dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI/QSPI/µWire/DSP Compatible
Standby Mode: 0.5 µA max
6-Lead SOT-23 Package and 8 lead µSOIC
APPLICATIONS
Battery Powered Systems
Medical Instruments
Ramote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
The AD7466/AD7467/AD7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. The parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. The parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. There are no pipelined delays
associated with the part.
The AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
The reference for the part is taken internally from VDD.
This allows the widest dynamic input range to the ADC.
Thus the analog input range for the part is 0 to VDD. The
conversion rate is determined by the SCLK.
FUNCTIONAL BLOCK DIAGRAM
VDD
12/10/8-BIT
VIN T/H SUCCESSIVE
APPROXIMATION
ADC
CONTROL LOGIC
AD7466/67/68
GND
SCLK
SDATA
CS
PRODUCT HIGHLIGHTS
1. Specified for Supply voltages of 1.8 V to 3.6 V
2. 8/10/12-Bit ADCs in a SOT-23 package.
3. High Throughput with Low Power Consumption
4. Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
5. Reference derived from the power supply.
6. No Pipeline Delay
The part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
REV. PrC 07/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001






AD7466 Datasheet, Funktion
pecifications
AD7466/AD7467/AD7468
PIN FUNCTION DESCRIPTION
Pin Pin
No. Mnemonic
6 CS
1 VDD
2 GND
3 VIN
5 SDATA
4 SCLK
Function
Chip Select. Active low logic input. This input provides the dual function of initiating con-
versions on the AD7466/AD7467/AD7468 and also frames the serial data transfer.
Power Supply Input. The VDD range for the AD7466/67/68 is from +1.8 V to +3.6 V.
Analog Ground. Ground reference point for all circuitry on the AD7466/AD7467/AD7468.
All analog input signals should be referred to this GND voltage.
Analog Input. Single-ended analog input channel. The input range is 0 to VDD.
Data Out. Logic Output. The conversion result from the AD7466/AD7467/AD7468 is pro-
vided on this output as a serial data stream. The bits are clocked out on the falling edge of
the SCLK input. The data stream from the AD7466 consists of four leading zeros followed
by the 12 bits of conversion data which is provided MSB first. The data stream for the
AD7467 consists of four leading zeros followed by 10 bits of data. The datastream for the
AD7468 consists of four leading zeros followed by 8 bits of data.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7466/AD7467/AD7468 conver-
sion process.
ORDERING GUIDE
Model
Temperature
Range
Linearity
Error (LSB)1
Package
Option2
AD7466BRT
AD7467BRT
AD7468BRT
AD7466BRM
AD7467BRM
AD7468BRM
EVAL-AD7466CB3
EVAL-AD7467CB3
EVAL-CONTROL BRD24
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±1 max
±1 max
±0.5 max
±1 max
±1 max
±0.5 max
RT-6
RT-6
RT-6
RM-8
RM-8
RM-8
NOTES
1Linearity Error here refers to integral linearity error.
2RT = SOT-23, RM = µSOIC.
3This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
4This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Branding
Information
CLB
CMB
CNB
CQB
CRB
CSB
AD7466/67/68 PINCONFIGURATION
AD7466/67/68 SOT-23
VDD 1
GND 2
VIN 3
AD7466/7/8
TOP VIEW
(Not to Scale)
6 CS
5 SDATA
4 SCLK
AD7466/67/68 µSOIC
CS 1
SDATA 2 AD7466/7/8
SCLK 3 TOP VIEW
NC 4 (Not to Scale)
8 VDD
7 GND
6 VIN
5 NC
–6– REV. PrC

6 Page









AD7466 pdf, datenblatt
pecifications
AD7466/AD7467/AD7468
SERIAL INTERFACE
Figure 15, 16, 17 show the detailed timing diagram for
serial interfacing to the AD7466/AD7467/AD7468.The
serial clock provides the conversion clock and also con-
trols the transfer of information from the ADC during a
conversion.
On the CS falling edge the part begins to power up. The
falling edge of CS puts the track and hold into track mode
and takes the bus out of tristate. The conversion is also
initiated at this point and will require 16 SCLK cycles to
complete. On the third SCLK falling edge the part should
be fully powered up, as shown in figure 15 at point B. On
the third SCLK falling edge after the CS falling edge the
track and hold will return to hold. On the 16th SCLK
falling edge the SDATA line will go back into tristate and
the AD7466 will enter power down. If the rising edge of
CS occurs before 16 SCLKs have elapsed then the conver-
sion will be terminated and the SDATA line will go back
into tri-state and the part will enter power down, otherwise
SDATA returns to tri-state on the 16th SCLK falling
edge as shown in Figure 15. Sixteen serial clock cycles
are required to perform the conversion process and to
access data from the AD7466.
For the AD7467, the fourteenth SCLK falling edge will
cause the SDATA line to go back into tri-state and the
part will enter powerdown. If the rising edge of CS occurs
before 14 SCLKs have elapsed then the conversion will be
terminated and the SDATA line will go back into tri-state
and the AD7467 will enter powerdown, otherwise SDATA
returns to tri-state on the 14th SCLK falling edge as
ahown in figure 16. Fourteen serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7467.
For the AD7468, the 12th SCLK falling edge will cause
the SDATA line to go back into tri-state and the part will
enter powerdown. If the rising edge of CS occurs before
12 SCLKs have elapsed then the conversion will be termi-
nated and the SDATA line will go back into tri-state and
the AD7468 will enter powerdown, otherwise SDATA
returns to tri-state on the 12th SCLK falling edge as
ahown in figure 17. Twelve serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7468.
CS going low provides the first leading zero to be read in
by the microcontroller or DSP. The remaining data is
then clocked out by subsequent SCLK falling edges be-
ginning with the 2nd leading zero, thus the first falling
clock edge on the serial clock has the first leading zero
provided and also clocks out the second leading zero. For
the Ad7466 the final bit in the data transfer is valid on the
sixteenth falling edge, having being clocked out on the
previous (15th) falling edge.
CS
SCLK
t2
1
B
23
tconvert
t6
45
SDATA
3-STATE
t3
Z ZERO
ZERO
ZERO
4 LEADING ZERO'S
t4
DB11
t7
DB10
13 14
t5
DB2
DB1
15
t8
16
DB0
Figure 15. AD7466 Serial Interface Timing Diagram
tquie
t
3-STATE
CS
SCLK
t2
1
B
23
tc on v ert
t6
45
SDATA
3-STATE
t3
Z ZERO ZERO ZERO
4 LEAD IN G ZERO'S
t4
DB9
t7
DB8
13 14
t5 t8
DB0
tquiet
3-STATE
Figure 16. AD7467 Serial Interface Timing Diagram
CS
SCLK
t2
1
B
23
SDATA
3-STATE
t3
Z ZERO ZERO ZERO
4 LEADING ZERO'S
tconvert
t6
4
t4
t5
11
t7
DB7 DB0
8 BITS OF DATA
12
t8
tquiet
3-STATE
Figure 17. AD7468 Serial Interface Timing Diagram
–12–
REV. PrC

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