PDF AD73322 Data sheet ( Hoja de datos )

Número de pieza	AD73322
Descripción	Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de AD73322 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! a Low Cost, Low Power CMOS General-Purpose Dual Analog Front End FEATURES Two 16-Bit A/D Converters Two 16-Bit D/A Converters Programmable Input/Output Sample Rates 78 dB ADC SNR 77 dB DAC SNR 64 kS/s Maximum Sample Rate –90 dB Crosstalk Low Group Delay (25 ␮s Typ per ADC Channel, 50 ␮s Typ per DAC Channel) Programmable Input/Output Gain Flexible Serial Port which Allows Up to Four Dual Codecs to be Connected in Cascade Giving Eight I/O Channels Single (+2.7 V to +5.5 V) Supply Operation 73 mW Typ Power Consumption at 3.0 V On-Chip Reference 28-Lead SOIC and 44-Lead LQFP Packages APPLICATIONS General Purpose Analog I/O Speech Processing Cordless and Personal Communications Telephony Active Control of Sound and Vibration Data Communications Wireless Local Loop GENERAL DESCRIPTION The AD73322 is a dual front-end processor for general-purpose applications including speech and telephony. It features two 16-bit A/D conversion channels and two 16-bit D/A conversion channels. Each channel provides 77␣ dB signal-to-noise ratio over a voiceband signal bandwidth. It also features an input-to- output gain network in both the analog and digital domains. This is featured on both codecs and can be used for impedance matching or scaling when interfacing to Subscriber Line Inter- face Circuits (SLICs). The AD73322 is particularly suitable for a variety of applica- tions in the speech and telephony area, including low bit rate, high quality compression, speech enhancement, recognition, and synthesis. The low group delay characteristic of the part makes it suitable for single or multichannel active control applications. VFBP1 VINP1 VINN1 VFBN1 VOUTP1 VOUTN1 REFOUT REFCAP VFBP2 VINP2 VINN2 VFBN2 VOUTP2 VOUTN2 AD73322 FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 DVDD AD73322 ADC CHANNEL 1 SDI SDIFS DAC CHANNEL 1 REFERENCE SPORT SCLK SE RESET ADC CHANNEL 2 MCLK DAC CHANNEL 2 SDOFS SDO AGND1 AGND2 DGND The A/D and D/A conversion channels feature programmable input/output gains with ranges of 38 dB and 21 dB respectively. An on-chip reference voltage is included to allow single-supply operation. This reference is programmable to accommodate either 3 V or 5 V operation. The sampling rate of the codecs is programmable with four separate settings, offering 64 kHz, 32 kHz, 16 kHz and 8 kHz sampling rates (from a master clock of 16.384 MHz). A serial port (SPORT) allows easy interfacing of single or cas- caded devices to industry standard DSP engines. The SPORT transfer rate is programmable to allow interfacing to both fast and slow DSP engines. The AD73322 is available in 28-lead SOIC and 44-lead LQFP packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page AD73322 SPECIFICATIONS1 (AVDD = +5 V ؎ 10%; DVDD = +5 V ؎ 10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted) Parameter AD73322A Min Typ Max Units Test Conditions/Comments REFERENCE REFCAP Absolute Voltage, VREFCAP REFCAP TC REFOUT Typical Output Impedance Absolute Voltage, VREFOUT Minimum Load Resistance Maximum Load Capacitance 1.2 2.4 50 130 1.2 2.4 2 V 5VEN = 0 V 5VEN = 1 ppm/°C 0.1 µF Capacitor Required from REFCAP to AGND2 Ω V 5VEN = 0, Unloaded V 5VEN = 1, Unloaded kΩ 5VEN = 1 100 pF INPUT AMPLIFIER Offset Maximum Output Swing Feedback Resistance Feedback Capacitance ± 1.0 3.156 50 100 mV V Max Output Swing = (3.156/2.4) × VREFCAP kΩ fC = 32 kHz pF ANALOG GAIN TAP Gain at Maximum Setting Gain at Minimum Setting Gain Resolution Gain Accuracy Settling Time Delay ADC SPECIFICATIONS Maximum Input Range at VIN2, 3 Nominal Reference Level at VIN (0 dBm0) Absolute Gain PGA = 0 dB PGA = 38 dB Gain Tracking Error Signal to (Noise + Distortion) PGA = 0 dB PGA = 38 dB Total Harmonic Distortion PGA = 0 dB PGA = 38 dB Intermodulation Distortion Idle Channel Noise Crosstalk ADC-to-DAC ADC-to-ADC DC Offset Power Supply Rejection Group Delay4, 5 Input Resistance at PGA2, 4, 6 +1 –1 5 ±1 1.0 0.5 3.156 3.17 2.1908 0 0.4 –0.7 ± 0.1 78 78 57 56 –84 –70 –65 –71 –100 –100 –70 +10 –65 25 20 Bits % µs µs V p-p dBm V p-p dBm dB dB dB dB dB dB dB dB dB dB dBm0 dB dB dB mV dB µs kΩ Gain Step Size = 0.0625 Output Unloaded Tap Gain Change of –FS to +FS 5VEN = 1 Measured Differentially Max Input Swing = (3.156/2.4) × VREFCAP Measured Differentially 1.0 kHz, 0 dBm0 1.0 kHz, 0 dBm0 1.0 kHz, +3 dBm0 to –50 dBm0 Refer to Figure 7 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 8 kHz 0 Hz to fSAMP/2; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 64 kHz 300 Hz to 3400 Hz; fSAMP = 64 kHz PGA = 0 dB PGA = 0 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle. Input Amplifiers Bypassed Input Amplifiers Included in Channel PGA = 0 dB Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave 64 kHz Output Sample Rate Input Amplifiers Bypassed REV. B –5– 5 Page Mnemonic VINP1 VFBP1 VINN1 VFBN1 REFOUT REFCAP AVDD2 AGND2 DGND DVDD RESET SCLK MCLK SDO SDOFS SDIFS SDI SE AGND1 AVDD1 VOUTP2 VOUTN2 VOUTP1 VOUTN1 VINP2 VFBP2 VINN2 VFBN2 AD73322 PIN FUNCTION DESCRIPTIONS Function Analog Input to the inverting input amplifier on Channel 1’s positive input. Feedback Connection from the output of the inverting amplifier on Channel 1’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the positive input of Channel 1’s sigma-delta modulator. Analog Input to the inverting input amplifier on Channel 1’s negative input. Feedback connection from the output of the inverting amplifier on Channel 1’s negative input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 1’s sigma-delta modulator. Buffered Reference Output, which has a nominal value of 1.2 V or 2.4 V, the value being dependent on the status of Bit 5VEN (CRC:7). As the reference is common to the two codec units, the reference value is set by the wired OR of the CRC:7 bits in Control Register C of each channel. A bypass capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin. Analog Power Supply Connection. Analog Ground/Substrate Connection2. Digital Ground/Substrate Connection. Digital Power Supply Connection. Active Low Reset Signal. This input resets the entire chip, resetting the control registers and clearing the digital circuitry. Serial Clock Output whose rate determines the serial transfer rate to/from the codec. It is used to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is equal to the frequency of the master clock (MCLK) divided by an integer number—this integer number being the product of the external mas- ter clock rate divider and the serial clock rate divider. Master Clock Input. MCLK is driven from an external clock signal. Serial Data Output. Both data and control information may be output on this pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low. Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK. SDOFS is in three-state when SE is low. Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK period be- fore the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and is ignored when SE is low. Serial Data Input. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low. SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled internally in order to decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are at their original values (before SE was brought low); however, the timing counters and other internal registers are at their reset values. Analog Ground/Substrate Connection. Analog Power Supply Connection. Analog Output from the Positive Terminal of Output Channel 2. Analog Output from the Negative Terminal of Output Channel 2. Analog Output from the Positive Terminal of Output Channel 1. Analog Output from the Negative Terminal of Output Channel 1. Analog Input to the inverting input amplifier on Channel 2’s positive input. Feedback connection from the output of the inverting amplifier on Channel 2’s positive input. When the input amplifiers are bypassed, this pin allows direct access to the positive input of Channel 2’s sigma-delta modulator. Analog Input to the inverting input amplifier on Channel 2’s negative input. Feedback connection from the output of the inverting amplifier on Channel 2’s negative input. When the input amplifiers are bypassed, this pin allows direct access to the negative input of Channel 2’s sigma-delta modulator. REV. B –11– 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet AD73322.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AD73322	Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End	Analog Devices
AD73322L	Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar