Datenblatt-pdf.com


AD73311L Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD73311L
Beschreibung Low Cost/ Low Power CMOS General Purpose Analog Front End
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD73311L Datasheet, Funktion
a
Low Cost, Low Power CMOS
General Purpose Analog Front End
AD73311L
FEATURES
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
76 dB ADC SNR
77 dB DAC SNR
Programmable Sampling Rate
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 ms Typ per ADC Channel,
50 ms Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port Which Allows Up to Eight Devices
to Be Connected in Cascade
Single (+3 V) Supply Operation
33 mW Max Power Consumption at 2.7 V
On-Chip Reference
20-Lead SOIC/SSOP/TSSOP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
GENERAL DESCRIPTION
The AD73311L is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70 dB signal-to-noise ratio over
a voiceband signal bandwidth. The nal channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital ltering in a DSP engine.
The AD73311L is suitable for a variety of applications in the
speech and telephony area, including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.
The gains of the A/D and D/A conversion channels are program-
mable over 38 dB and 21 dB ranges respectively. An on-chip
reference voltage is included to allow single supply operation.
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines.
The AD73311L is available in 20-lead SOIC, SSOP and
TSSOP packages.
AVDD1
FUNCTIONAL BLOCK DIAGRAM
AVDD2
DVDD
VINP
VINN
ANALOG
LOOPBACK/
SINGLE-ENDED
ENABLE
0/38dB
PGA
VOUTP
VOUTN
REFCAP
REFOUT
+6/–15dB
PGA
CONTINUOUS
TIME
LOW-PASS FILTER
REFERENCE
ANALOG
SIGMA-DELTA
MODULATOR
DECIMATOR
SWITCHED-
CAPACITOR
LOW-PASS FILTER
1-BIT
DAC
DIGITAL
SIGMA-DELTA
MODULATOR
SERIAL
I/O
PORT
INTERPOLATOR
AD73311L
AGND1
AGND2
DGND
SDI
SDIFS
SCLK
SDO
SDOFS
SE
MCLK
RESET
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD73311L Datasheet, Funktion
AD73311L
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . 0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . 0.3 V to (DVDD + 0.3 V)
Analog I/O Voltage to AGND . . . 0.3 V to (AVDD + 0.3 V)
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . 40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . 65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
SSOP, θJA Thermal Impedance . . . . . . . . . . . . . . . . 126°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
TSSOP, θJA Thermal Impedance . . . . . . . . . . . . . . . 143°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specication is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
PIN CONFIGURATION
VOUTP 1
20 SE
VOUTN 2
19 SDI
AVDD1 3
18 SDIFS
AGND1 4
17 SDOFS
VINP 5 AD73311L 16 SDO
VINN
6
TOP VIEW
(Not to Scale)
15
MCLK
REFOUT 7
14 SCLK
REFCAP 8
13 RESET
AVDD2 9
12 DVDD
AGND2 10
11 DGND
ORDERING GUIDE
Model
Temperature
Range
Package
Option1
AD73311LAR
AD73311LARS
AD73311LARU
EVAL-AD73311LEB
40°C to +105°C
40°C to +105°C
40°C to +105°C
Evaluation Board2
R-20
RS-20
RU-20
NOTES
1R = 0.3' Small Outline IC (SOIC), RS = Shrink Small Outline Package (SSOP),
RU = Thin Small Shrink Outline Package (TSSOP).
2The AD73311L evaluation board features a cascade of two codecs interfaced to
an ADSP-2185L DSP. The board features a DSP software monitor which
allows interface to a PC serial port.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73311L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. A

6 Page









AD73311L pdf, datenblatt
AD73311L
MCLK
(EXTERNAL)
MCLK
DIVIDER
DMCLK
(INTERNAL)
SE
RESET
SDIFS
SDI
3
SERIAL PORT
(SPORT)
SSEERRIIAALL REEGGISISTTEERR
88
88
SCLK
DIVIDER
SCLK
2
8
8
SDOFS
SDO
CONTROL
REGISTER A
CONTROL
REGISTER B
CONTROL
REGISTER C
CONTROL
REGISTER D
CONTROL
REGISTER E
CONTROL
REGISTER F
Figure 9. SPORT Block Diagram
SPORT Register Maps
There are two register banks for the AD73311L: the control
register bank and the data register bank. The control register
bank consists of six read/write registers, each eight bits wide.
Table IX shows the control register map for the AD73311L.
The rst two control registers, CRA and CRB, are reserved for
controlling the SPORT. They hold settings for parameters such
as bit rate, internal master clock rate and device count (used
when more than one AD73311L is connected in cascade from
a single SPORT). The other three registers; CRC, CRD and
CRE are used to hold control settings for the ADC, DAC,
Reference and Power Control sections of the device. Control
registers are written to on the negative edge of SCLK. The
data register bank consists of two 16-bit registers that are the
DAC and ADC registers.
Master Clock Divider
The AD73311L features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to
produce an internal master clock signal (DMCLK) that is used
to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table V shows
the division ratio corresponding to the various bit settings. The
default divider ratio is divide-by-one.
Table V. DMCLK (Internal) Rate Divider Settings
MCD2
0
0
0
0
1
1
1
1
MCD1
0
0
1
1
0
0
1
1
MCD0
0
1
0
1
0
1
0
1
DMCLK Rate
MCLK
MCLK/2
MCLK/3
MCLK/4
MCLK/5
MCLK
MCLK
MCLK
Serial Clock Rate Divider
The AD73311L features a programmable serial clock divider that
allows users to match the serial clock (SCLK) rate of the data to
that of the DSP engine or host processor. The maximum SCLK
rate available is DMCLK and the other available rates are:
DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
is programmable by setting bits CRB:23. Table VI shows the
serial clock rate corresponding to the various bit settings.
Table VI. SCLK Rate Divider Settings
SCD1
0
0
1
1
SCD0
0
1
0
1
SCLK Rate
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
Sample Rate Divider
The AD73311L features a programmable sample rate divider
that allows users flexibility in matching the codecs ADC and
DAC sample rates to the needs of the DSP software. The maxi-
mum sample rate available is DMCLK/256 which offers the
lowest conversion group delay, while the other available rates
are: DMCLK/512, DMCLK/1024 and DMCLK/2048. The
slowest rate (DMCLK/2048) is the default sample rate. The
sample rate divider is programmable by setting bits CRB:0-1.
Table VII shows the sample rate corresponding to the various
bit settings.
Table VII. Sample Rate Divider Settings
DIR1
0
0
1
1
DIR0
0
1
0
1
SCLK Rate
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
DAC Advance Register
The loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance eld in Control
Register E (CRE:04). The eld is ve bits wide, allowing 31
increments of weight 1/(DMCLK/8); see Table VIII. In certain
circumstances this can reduce the group delay when the ADC
and DAC are used to process data in series. Appendix E details
how the DAC advance feature can be used.
NOTE: The DAC advance register should be changed before
the DAC section is powered up.
–12–
REV. A

12 Page





SeitenGesamt 30 Seiten
PDF Download[ AD73311L Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD73311Low Cost/ Low Power CMOS General Purpose Analog Front EndAnalog Devices
Analog Devices
AD73311LLow Cost/ Low Power CMOS General Purpose Analog Front EndAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche