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PDF AD7305 Data sheet ( Hoja de datos )
| Número de pieza | AD7305 | |
| Descripción | +3 V/+5 V/ Rail-to-Rail Quad/ 8-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Four 8-bit DACs in one package
+3 V, +5 V, and ±5 V operation
Rail-to-rail REF input to voltage output swing
2.6 MHz reference multiplying bandwidth
Internal power-on reset
SPI serial interface-compatible—AD7304
Fast parallel interface—AD7305
40 µA power shutdown
APPLICATIONS
Automotive output span voltage
Instrumentation, digitally controlled calibration
Pin-compatible AD7226 replacement when VDD < 5.5 V
GENERAL DESCRIPTION
The AD7304/AD73051 are quad, 8-bit DACs that operate from
a single +3 V to +5 V supply, or ±5 V supplies. The AD7304 has
a serial interface, while the AD7305 has a parallel interface.
Internal precision buffers swing rail-to-rail. The reference input
range includes both supply rails, allowing for positive or negative
full-scale output voltages. Operation is guaranteed over the
supply voltage range of 2.7 V to 5.5 V, consuming less than
9 mW from a 3 V supply.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail VREF input to
DAC VOUT allows for a full-scale voltage set equal to the positive
supply, VDD, the negative supply, VSS, or any value in between.
The AD7304’s doubled-buffered serial data interface offers high
speed, 3-wire, SPI®-, and microcontroller-compatible inputs
using data in (SDI), clock (CLK), and chip select (CS) pins.
Additionally, an internal power-on reset sets the output to zero
scale.
The parallel input AD7305 uses a standard address decode
along with the WR control line to load data into the input
registers.
The double-buffered architecture allows all four input registers
to be preloaded with new values, followed by an LDAC control
strobe that copies all the new data into the DAC registers,
thereby updating the analog output values.
_____________________________________________________
1 Protected under Patent No. 5684481.
3 V/5 V, Rail-to-Rail
Quad, 8-Bit DAC
AD7304/AD7305
FUNCTIONAL BLOCK DIAGRAMS
VDD
VREFB VREFA
CS
SDI/SHDN
CLK
PWR-ON
RESET
8
INPUT 8 DAC A 8
REG A
REG
INPUT 8 DAC B 8
REG B
REG
SERIAL
REG
INPUT 8 DAC C 8
REG C
REG
INPUT 8 DAC D 8
REG D
REG
DAC A
DAC B
DAC C
DAC D
AD7304
VOUTA
VOUTB
VOUTC
VOUTD
VSS GND
CLR LDAC VREFC VREFD
Figure 1.
VDD
VREF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
WR
A0/SHDN
A1
PWR-ON
RESET
8
INPUT 8 DAC A 8
REG A
REG
INPUT 8 DAC B 8
REG B
REG
8
DECODE
INPUT 8 DAC C 8
REG C
REG
INPUT 8 DAC D 8
REG D
REG
DAC A
DAC B
DAC C
DAC D
AD7305
LDAC
Figure 2.
VSS
GND
VOUTA
VOUTB
VOUTC
VOUTD
When operating from less than 5.5 V, the AD7305 is
pin-compatible with the popular industry-standard AD7226.
An internal power-on reset places both parts in the zero-scale
state at turn-on. A 40 µA power shutdown (SHDN) feature is
activated on both parts by three-stating the SDI/SHDN pin on
the AD7304 and three-stating the A0/SHDN address pin on the
AD7305.
The AD7304/AD7305 are specified over the extended industrial
−40°C to +85°C and the automotive −40°C to +125°C
temperature ranges. AD7304s are available in a wide-body
16-lead SOIC (R-16) package. The parallel input AD7305 is
available in the wide-body 20-lead SOIC (R-20) surface-mount
package. For ultracompact applications, the thin 1.1 mm,
16-lead TSSOP (RU-16) package is available for the AD7304,
while the 20-lead TSSOP (RU-20) houses the AD7305.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD7304/AD7305
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
VSS to GND
VREFX to GND
Logic Inputs to GND
VOUTX to GND
IOUT Short-Circuit to GND
Package Power Dissipation
Thermal Resistance θJA
16-Lead SOIC Package (R-16)
16-Lead TSSOP Package (RU-16)
20-Lead SOIC Package (R-20)
20-Lead TSSOP Package (RU-20)
Maximum Junction Temperature (TJ MAX)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
R-16, R-20, RU-16, RU-20 (Vapor Phase, 60 sec)
R-16, R-20, RU-16, RU-20 (Infrared, 15 sec)
Rating
−0.3 V, +8 V
+0.3 V, −8 V
VSS, VDD
−0.3 V, VDD + 0.3 V
−0.3 V, VDD + 0.3 V
50 mA
(TJ MAX – TA)/θJA
73°C/W
180°C/W
74°C/W
155°C/W
150°C
−40°C to +85°C
−65°C to +150°C
235°C
220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 20
5 Page 
VOUT
VDD = 5V
VREF = 4V
DATA = 0x00
0xFF
CS
2µs/DIV
Figure 16. Large-Signal Settling Time
0V
5V
0V
VREFIN
(±5V @
50kHz)
VOUTA
DATA = 0xFF
+5V
0V
–5V
+5V
0V
–5V
2µs/DIV
Figure 17. Multiplying Mode Step Response and Output Slew Rate
6
VDD = +5V
VSS = –5V
DATA = 0xFF
4 VREF = 100mV rms
0
f–3dB = 2.6MHz
–4
–6
–8
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 18. Multiplying Mode Gain vs. Frequency
AD7304/AD7305
NO LOAD
RL = 70kΩ
RL = 10kΩ
VDD = 5V
CL = 150pF
CS
VOUT
5µs/DIV
Figure 19. Time to Shutdown
CS
IDD
1mA/V
VDD = 5V
VOUT
Figure 20. Shutdown Recovery Time (Wakeup)
10
VDD = +5V
VSS = –5V
1
0.1
0.01
0.001
10m 1 2 3 4 5 6 7 8 9
VREF AMPLITUDE (V p-p)
Figure 21. THD vs. Reference Input Amplitude
10
Rev. C | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7305.PDF ] | |
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