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AD7008 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7008
Beschreibung CMOS DDS Modulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD7008 Datasheet, Funktion
a
CMOS
DDS Modulator
AD7008
FEATURES
Single +5 V Supply
32-Bit Phase Accumulator
On-Chip COSINE and SINE Look-Up Tables
On-Chip 10-Bit DAC
Frequency, Phase and Amplitude Modulation
Parallel and Serial Loading
Software and Hardware Power Down Options
20 MHz and 50 MHz Speed Grades
44-Pin PLCC
APPLICATIONS
Frequency Synthesizers
Frequency, Phase or Amplitude Modulators
DDS Tuning
Digital Modulation
PRODUCT DESCRIPTION
The AD7008 direct digital synthesis chip is a numerically con-
trolled oscillator employing a 32-bit phase accumulator, sine and
cosine look-up tables and a 10-bit D/A converter integrated on a
single CMOS chip. Modulation capabilities are provided for
phase modulation, frequency modulation, and both in-phase and
quadrature amplitude modulation suitable for QAM and SSB
generation.
Clock rates up to 20 MHz and 50 MHz are supported. Fre-
quency accuracy can be controlled to one part in 4 billion.
Modulation may be effected by loading registers either through
the parallel microprocessor interface or the serial interface. A
frequency-select pin permits selection between two frequencies
on a per cycle basis.
The serial and parallel interfaces may be operated independently
and asynchronously from the DDS clock; the transfer control
signals are internally synchronized to prevent metastability prob-
lems. The synchronizer can be bypassed to reduce the transfer
latency in the event that the microprocessor clock is synchro-
nous with the DDS clock.
A power-down pin allows external control of a power-down
mode (also accessible through the microprocessor interface)
The AD7008 is available in 44-pin PLCC.
PRODUCT HIGHLIGHT
1. Low Power
2. DSP/µP Interface
3. Completely Integrated
CLOCK
FSELECT
SCLK
SDATA
FUNCTIONAL BLOCK DIAGRAM
VAA GND
FS ADJUST VREF
FREQ0 32
REG
32
MUX
32
12
Σ
FREQ1
REG
32
PHASE
ACCUMULATOR
12
Σ
12
32-BIT SERIAL REGISTER
PHASE REG
IQMOD [19:10]
10
10
SIN
SIN/COS
ROM
10
COS
10
10
Σ
10
10
IQMOD [9:0]
FULLSCALE
ADJUST
10-BIT DAC
32-BIT PARALLEL REGISTER
COMMAND REG
AD7008
COMP
IOUT
IOUT
MPU INTERFACE
TRANSFER LOGIC
D0
D15 WR CS
TC0
TC3 LOAD
TEST
RESET SLEEP
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD7008 Datasheet, Funktion
AD7008
14 PIPELINE DELAYS
PHASE
ACCUMULATOR
32
AD7008
REGISTER
AND
CONTROL
LOGIC
32
12
20
ACCUM RESET
SLEEP
AM ENABLE
12
13 PIPELINE DELAYS
PHASE
SUMMATION
12
SIN 10
ROM
COS 10
11 PIPELINE DELAYS
SIN/ COS
SUMMATION
10
10
10
9:0 19:10
DAC
IOUT/ IOUT
Figure 7. AD7008 CMOS DDS Modulator (See Table I)
SLEEP (37)
SCLK (41)
SDATA (42)
D0-D15
(19-26, 8-15)
WR (16)
CS (27)
DQ
x 32
32-BIT SERIAL
ASSEMBLY REGISTER
32-BIT PARALLEL
ASSEMBLY REGISTER
23:0
15:0 23:8
15:8 7:0
7:0
0 31:8
x 24
1
DQ
x 32
31:0
31:0
0
x 32
1
DQ
CLK
REGISTER
MUX
COMMAND REGISTER
3:0 D2
DQ
x4
AM ENABLE
DQ
CLK
CLK
DQ
CLK
D1 D Q SLEEP
CLK
D0 BUS MODE
D3 SYNCHRO LOGIC
LOAD (36)
FSEL (31)
TC0-TC3
(32-35)
D FLIP-FLOPS ARE MASTER SLAVE,
LATCHING DATA ON CLK RISING EDGE.
PASS FLIP-FLOPS ARE TRANSPARENT
WHEN THE CLOCK IS LOW.
6
TRANSFER CONTROL (TC) REGISTER
DQ
x6
PASS
DQ
x6
DQ
x6
DQ
x6
DQ
x6
0
x6
1
CLK
RESET (38)
RESET SYNCHRONIZATION
DQ
DQ
DQ
FSELECT
5
TC0
TC1
TC3
LOAD
TC3
TC2
TRANSFER DECODE
0
S1
2
E3
0
1
2
3
4
x5
CLK
DQ
x5
4
0
1
2
3
TC2 D Q
CLK
CLOCK (30)
CLK
CLK
Figure 8. AD7008 Register and Control Logic
FREQUENCY
REGISTERS
FREQ 0
32
DQ
CLK x 32
E
FREQ 1
32
DQ
CLK x 32
E
0 TO PHASE
x32
1 ACCUMULATOR
PHASE REGISTER
12
DQ
CLK x 12
E
TO PHASE
SUMMATION
IQ MOD REGISTER
10
DQ
x 20
CLK
E
TO SIN/COS
SUMMATION
ACCUMULATOR
RESET
–6– REV. B

6 Page









AD7008 pdf, datenblatt
AD7008–Typical Performance Characteristics
VREF
6
+5V
COMP
5
115
VREF TYP
TO DAC
AD7008
4
RSET
REF 5.0 dBm
10 dB/DIV
RANGE 5.0 dBm
OFFSET 4 640 000.0 Hz
–54.8 dB
Figure 17. Equivalent Reference Circuit
START 0 Hz
RBW 3 kHz
VBW 10 kHz
STOP 10 000 000.0 Hz
ST 2.4 SEC
Figure 20. fCLK = 20 MHz, fOUT = 5.1 MHz
REF 4.3 dBm
10 dB/DIV
RANGE 5.0 dBm
OFFSET 3 330 000.0 Hz
–63.6 dB
REF 4.3 dBm
10 dB/DIV
RANGE 5.0 dBm
OFFSET 6 320 000.0 Hz
–61.3 dB
START 0 Hz
RBW 3 kHz
VBW 10 kHz
STOP 10 000 000.0 Hz
ST 2.4 SEC
Figure 18. fCLK = 20 MHz, fOUT = 1.1 MHz
REF 4.3 dBm
10 dB/DIV
RANGE 5.0 dBm
OFFSET 4 500 000.0 Hz
–61.1 dB
START 0 Hz
RBW 3 kHz
VBW 10 kHz
STOP 10 000 000.0 Hz
ST 2.4 SEC
Figure 21. fCLK = 20 MHz, fOUT = 2.1 MHz
REF 5.0 dBm
10 dB/DIV
RANGE 5.0 dBm
OFFSET –490 000.0 Hz
–63.4 dB
START 0 Hz
RBW 3 kHz
VBW 10 kHz
STOP 10 000 000.0 Hz
ST 2.4 SEC
Figure 19. fCLK = 20 MHz, fOUT = 3.1 MHz
START 0 Hz
RBW 3 kHz
VBW 10 kHz
STOP 10 000 000.0 Hz
ST 2.4 SEC
Figure 22. fCLK = 20 MHz, fOUT = 4.1 MHz
–12–
REV. B

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