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PDF AD650 Data sheet ( Hoja de datos )
| Número de pieza | AD650 | |
| Descripción | Voltage-to-Frequency and Frequency-to-Voltage Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
V/F Conversion to 1 MHz
Reliable Monolithic Construction
Very Low Nonlinearity
0.002% typ at 10 kHz
0.005% typ at 100 kHz
0.07% typ at 1 MHz
Input Offset Trimmable to Zero
CMOS or TTL Compatible
Unipolar, Bipolar, or Differential V/F
V/F or F/V Conversion
Available in Surface Mount
MIL-STD-883 Compliant Versions Available
Voltage-to-Frequency and
Frequency-to-Voltage Converter
AD650
PIN CONFIGURATION
PRODUCT DESCRIPTION
The AD650 V/F/V (voltage-to-frequency or frequency-to-voltage
converter) provides a combination of high frequency operation
and low nonlinearity previously unavailable in monolithic form.
The inherent monotonicity of the V/F transfer function makes
the AD650 useful as a high-resolution analog-to-digital converter.
A flexible input configuration allows a wide variety of input volt-
age and current formats to be used, and an open-collector output
with separate digital ground allows simple interfacing to either
standard logic families or opto-couplers.
The linearity error of the AD650 is typically 20 ppm (0.002%
of full scale) and 50 ppm (0.005%) maximum at 10 kHz full
scale. This corresponds to approximately 14-bit linearity in an
analog-to-digital converter circuit. Higher full-scale frequencies
or longer count intervals can be used for higher resolution con-
versions. The AD650 has a useful dynamic range of six decades
allowing extremely high resolution measurements. Even at 1 MHz
full scale, linearity is guaranteed less than 1000 ppm (0.1%) on
the AD650KN, BD, and SD grades.
In addition to analog-to-digital conversion, the AD650 can be used
in isolated analog signal transmission applications, phased locked-
loop circuits, and precision stepper motor speed controllers. In
the F/V mode, the AD650 can be used in precision tachometer
and FM demodulator circuits.
The input signal range and full-scale output frequency are user-
programmable with two external capacitors and one resistor.
Input offset voltage can be trimmed to zero with an external
potentiometer.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The AD650JN and AD650KN are offered in a plastic 14-lead
DIP package. The AD650JP is available in a 20-lead plastic
leaded chip carrier (PLCC). Both plastic packaged versions of the
AD650 are specified for the commercial (0°C to +70°C) tempera-
ture range. For industrial temperature range (–25°C to +85°C)
applications, the AD650AD and AD650BD are offered in a
ceramic package. The AD650SD is specified for the full –55°C
to +125°C extended temperature range.
PRODUCT HIGHLIGHTS
1. In addition to very high linearity, the AD650 can operate at
full-scale output frequency up to 1 MHz. The combination of
these two features makes the AD650 an inexpensive solution
for applications requiring high resolution monotonic A/D
conversion.
2. The AD650 has a very versatile architecture that can be con-
figured to accommodate bipolar, unipolar, or differential
input voltages, or unipolar input currents.
3. TTL or CMOS compatibility is achieved using an open
collector frequency output. The pull-up resistor can be
connected to voltages up to +30 V, or +15 V or +5 V for
conventional CMOS or TTL logic levels.
4. The same components used for V/F conversion can also be
used for F/V conversion by adding a simple logic biasing net-
work and reconfiguring the AD650.
5. The AD650 provides separate analog and digital grounds.
This feature allows prevention of ground loops in real-world
applications.
6. The AD650 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD650/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD650
at analog ground is opened allowing that voltage to change. An
internal 0.5 mA current source connected to Pin 6 then draws
its current out of COS, causing the voltage at Pin 6 to decrease
linearly. At approximately –3.4 V, the one shot resets itself,
thereby ending the timed period and starting the V/F conversion
cycle over again. The total one shot time period can be written
mathematically as:
tOS
=
∆V COS
IDISCHARGE
+ TGATE
DELAY
substituting actual values quoted above,
(5)
tOS
=
–3.4 V × COS
–0.5 × 10–3A
+
300
× 10–9
sec
(6)
This simplifies into the timed period equation given above.
Figure 3a. Full-Scale Frequency vs. COS
COMPONENT SELECTION
Only four component values must be selected by the user. These
are input resistance RIN, timing capacitor COS, logic resistor R2,
and integration capacitor CINT. The first two determine the
input voltage and full-scale frequency, while the last two are
determined by other circuit considerations.
Of the four components to be selected, R2 is the easiest to
define. As a pull-up resistor, it should be chosen to limit the
current through the output transistor to 8 mA if a TTL maxi-
mum VOL of 0.4 V is desired. For example, if a 5 V logic supply
is used, R2 should be no smaller than 5 V/8 mA or 625 Ω. A
larger value can be used if desired.
RIN and COS are the only two parameters available to set the
full- scale frequency to accommodate the given signal range.
The “swing” variable that is affected by the choice of RIN and
COS is nonlinearity. The selection guide of Figure 3 shows this
quite graphically. In general, larger values of COS and lower
full-scale input currents (higher values of RIN) provide better
linearity. In Figure 3, the implications of four different choices
of RIN are shown. Although the selection guide is set up for a
unipolar configuration with a zero to 10 V input signal range,
the results can be extended to other configurations and input
signal ranges. For a full scale frequency of 100 kHz (corre-
sponding to 10 V input), you can see that among the available
choices, RIN = 20 k and COS = 620 pF gives the lowest nonlin-
earity, 0.0038%. Also, if you wish to use the highest frequency
that will give the 20 ppm minimum nonlinearity, it is approxi-
mately 33 kHz (40.2 kΩ and 1000 pF).
For input signal spans other than 10 V, the input resistance
must be scaled proportionately. For example, if 100 kΩ is called
out for a 0 V–10 V span, 10k would be used with a 0 V–1 V
span, or 200 kΩ with a ± 10 V bipolar connection.
The last component to be selected is the integration capacitor
CINT. In almost all cases, the best value for CINT can be calcu-
lated using the equation:
CINT
=
10–4F / sec
f MAX
(1000
pF
minimum)
(7)
When the proper value for CINT is used, the charge balance
architecture of the AD650 provides continuous integration of
the input signal, hence large amounts of noise and interference
Figure 3b. Typical Nonlinearity vs. COS
can be rejected. If the output frequency is measured by counting
pulses during a constant gate period, the integration provides
infinite normal-mode rejection for frequencies corresponding to
the gate period and its harmonics. However, if the integrator
stage becomes saturated by an excessively large noise pulse, the
continuous integration of the signal will be interrupted, allowing
the noise to appear at the output. If the approximate amount of
noise that will appear on CINT is known (VNOISE), the value of
CINT can be checked using the following inequality:
CINT
>
tOS ×1×10–3 A
+V S – 3V –V NOISE
(8)
For example, consider an application calling for a maximum
frequency of 75 kHz, a 0 volt–1 volt signal range, and supply
voltages of only ± 9 volts. The component selection guide of Fig-
ure 3 is used to select 2.0 kΩ for RIN and 1000 pF for COS. This
results in a one shot time period of approximately 7 µs. Sub-
stituting 75 kHz into equation 7 yields a value of 1300 pF for
CINT. When the input signal is near zero, 1 mA flows through the
integration capacitor to the switched current sink during the reset
phase, causing the voltage across CINT to increase by approximately
5.5 volts. Since the integrator output stage requires approximately
3 volts head room for proper operation, only 0.5 volt margin
remains for integrating extraneous noise on the signal line. A
negative noise pulse at this time might saturate the integrator,
causing an error in signal integration. Increasing CINT to 1500 pF
or 2000 pF will provide much more noise margin, thereby elimi-
nating this potential trouble spot.
REV. C
–5–
5 Page 
AD650
output cannot change very rapidly due to the integrator time
constant formed by CINT and RIN. While it is possible to decrease
the integrator time constant to provide faster settling of the
F-to-V output voltage, the carrier feedthrough will then be
larger. For signal frequency response in excess of 2 kHz, a phase
locked F/V conversion technique such as the one shown in Fig-
ure 14 is recommended.
the AD650 slightly, driving the system towards synchronization.
In a similar manner, if the input carrier lags the output carrier,
the integrator will be forced down slightly to synchronize the
two signals.
Using a mathematical approach, the ± 25 µA pulses from the
phase detector are incorporated into the phase detector gain, Kd.
Using a mathematical approach, the ± 25 µA pulses from the
phase detector are incorporated into the phase detector gain, Kd.
Kd
=
25 µA
2π
=
4
× 10–6
amperes /radian
(9)
Also, the V/F converter is configured to produce 1 MHz in
response to a 10 volt input, so its gain Ko, is:
Ko
=
2 π × 1 × 106 Hz
10 V
= 6.3 × 105
radians
volt • sec
(10)
The dynamics of the phase relationship between the input and
output signals can be characterized as a second order system
with natural frequency ωn:
Figure 14. Phase Locked Loop F/V Conversion
In a phase locked loop circuit, the oscillator is driven to a frequency
and phase equal to an input reference signal. In applications
such as a synthesizer, the oscillator output frequency is first pro-
cessed through a programmable “divide by N” before being
applied to the phase detector as feedback. Here the oscillator
frequency is forced to be equal to “N times” the reference fre-
quency and it is this frequency output which is the desired
output signal and not a voltage. In this case, the AD650 offers
compact size and wide dynamic range.
In signal recovery applications of a PLL, the desired output sig-
nal is the voltage applied to the oscillator. In these situations a
linear relationship between the input frequency and the output
voltage is desired; the AD650 makes a superb oscillator for FM
demodulation. The wide dynamic range and outstanding linearity
of the AD650 VFC allow simple embodiment of high perfor-
mance analog signal isolation or telemetry systems. The circuit
shown in Figure 14 uses a digital phase detector which also pro-
vides proper feedback in the event of unequal frequencies. Such
phase-frequency detectors (PFDs) are available in integrated
form. For a full discussion of phase lock loop circuits see
Reference 3.
An analysis of this circuit must begin at the 7474 dual D flip
flop. When the input carrier matches the output carrier in both
phase and frequency, the Q outputs of the flip flops will rise at
exactly the same time. With two zeros, then two ones on the
inputs of the exclusive or (XOR) gate, the output will remain
low keeping the DMOS FET switched off. Also, the NAND
gate will go low resetting the flip-flops to zero. Throughout the
entire cycle just described, the DMOS integrator gate remained
off, allowing the voltage at the integrator output to remain
unchanged from the previous cycle. However, if the input carrier
leads the output carrier by a few degrees, the XOR gate will be
turned on for the small time span that the two signals are mis-
matched. Since Q2 will be low during the mismatch time, a
negative current will be fed into the integrator, causing its out-
put voltage to rise. This in turn will increase the frequency of
3“Phase lock Techniques,” 2nd Edition, by F.M. Gardner, (John Wiley and
Sons, 1979)
and damping factor
ωn =
KoKd
C
(11)
ζ= R
C KoKd
2
(12)
For the values shown in Figure 14, these relations simplify to a
natural frequency of 35 kHz with a damping factor of 0.8.
For those desiring a simple approach to determining component
values for other PLL frequencies and VFC full-scale voltage, the
following cookbook steps can be used:
1. Determine Ko (in units of radians per volt second) from the
maximum input carrier frequency FMAX (in hertz) and the
maximum output voltage VMAX.
Ko
=
2
π × FMAX
VMAX
(13)
2. Calculate a value for C based upon the desired loop band-
width, fn. Note that this is the desired frequency range of the
output signal. The loop bandwidth (fn) is not the maximum
carrier frequency (fMAX): the signal may be very narrow even
though it is transmitted over a 1 MHz carrier.
C = Ko •1 × 10–7 V • F
fn2 Rad • sec
C units FARADS
fn units HERTZ (14)
Ko units RAD/VOLT•SEC
3. Calculate R to yield a damping factor of approximately 0.8
using this equation:
R = fn • 2.5 × 106 Rad • Ω
Ko V
R units OHMS
fn units HERTZ (15)
Ko units RAD/VOLT•SEC
If in actual operation the PLL overshoots or hunts excessively
before reaching a final value, the damping factor may be raised
by increasing the value of R. Conversely, if the PLL is over-
damped, a smaller value of R should be used.
REV. C
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD650.PDF ] | |
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