Datenblatt-pdf.com


AD642 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD642
Beschreibung Precision/ Low Cost Dual BiFET Op Amp
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 6 Seiten
AD642 Datasheet, Funktion
a
FEATURES
Matched Offset Voltage
Matched Offset Voltage Over Temperature
Matched Bias Current
Crosstalk: –124 dB @ 1 kHz
Low Bias Current: 35 pA max Warmed Up
Low Offset Voltage: 500 V max
Low Input Voltage Noise: 2 V p-p
High Open Loop Gain
Low Quiescent Current: 2.8 mA max
Low Total Harmonic Distortion
Standard Dual Amplifier Pin Out
Available in Hermetic Metal Can Package and Chip Form
MIL-STD-883B Processing Available
Single Version Available: AD542
Precision, Low Cost
Dual BiFET Op Amp
AD642
PIN CONFIGURATION
PRODUCT DESCRIPTION
The AD642 is a pair of matched high speed monolithic BiFET
operational amplifier fabricated with the most advanced bipolar,
JFET and laser trimming technologies. The AD642 offers
matched bias currents that are significantly lower than currently
available monolithic dual FET input operational amplifiers:
35 pA max matched to 25 pA for the AD642K and L; 75 pA
max, matched to 35 pA for the AD642J and S. In addition, the
offset voltage is laser trimmed to less than 0.5 mV and matched
to 0.25 mV for the AD642L, 1.0 mV and matched to 0.5 mV for
the AD642K, utilizing Analog’s laser-wafer trimming (LWT)
process.
The tight matching and temperature tracking between the
operational amplifiers is achieved by ion-implanted JFETs and
laser-wafer trimming. Ion-implantation permits the fabrication of
precision, matched JFETs on a monolithic bipolar chip. The
optimizes the process to product matched bias currents which
have lower initial bias currents than other popular BiFET op
amps. Laser-wafer trimming each amplifier’s input offset voltage
assures tight initial match and combined with superior IC
processing guarantees offset voltage tracking over the tempera-
ture range.
The AD642 is recommended for applications in which excellent
ac and dc performance is required. The matched amplifiers
provide a low-cost solution for true instrumentation amplifiers,
log ratio amplifiers, and output amplifiers for four quadrant
multiplying D/A converters such as the AD7541.
The AD642 is available in four versions: the ‘‘J’’, ‘‘K’’ and ‘‘L,’’
all specified over the 0°C to +70°C temperature range and one
version, ‘‘S,’’ over the –55°C to +125°C extended operating
temperature range. All devices are packaged in the hermetically-
sealed, TO-99 metal can or available in chip form.
PRODUCT HIGHLIGHTS
1. The AD642 has tight matching specifications to ensure high
performance, eliminating the need to match individual
devices.
2. Analog Devices, unlike some manufacturers, specifies each
device for the maximum bias current at either input in the
warmed-up condition, thus assuring the user that the AD642
will meet its published specifications in actual use.
3. Laser-wafer-trimming reduces offset voltage to as low as
0.5 mV max and matched side to side to 0.25 mV
(AD642L), thus eliminating the need for external nulling.
4. Low voltage noise (2 µV, p-p), and high open loop gain
enhance the AD642’s performance as a precision op amp.
5. The standard dual amplifier pin out allows the AD642 to
replace lower performance duals without redesign.
6. The AD642 is available in chip form.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD642 Datasheet, Funktion
AADD664422
linearization of transducers having exponential outputs, and
analog computing, ranging from simple translation of natural
relationships in log form (e.g., computing absorbance as the log-
ratio of input currents), to the use of logarithms in facilitating
analog computation of terms involving arbitrary exponents and
multiterm products and ratios.
The picoamp level input current and low offset voltage of the
AD642 make it suitable for wide dynamic range log amplifiers.
Figure 28 is a schematic of a log ratio circuit employing the
AD642 that can achieve less than 1% conformance error over 5
decades of current input, 1 nA to 100 µA. For voltage inputs,
the dynamic range is typically 50 mV to 10 V for 1% error
limited on the low end by the amplifier’s input offset voltage.
V2 = –10.00 V and adjust “Balance” for VOUT = 0.00 V. Next
apply V1 = –10.00 V, V2 = –1.00 V and adjust gain for VOUT =
+1.00 V. Repeat this procedure until gain and balance readings
are within 2 mV of ideal values.
The low input bias current (35 pA) and low noise characteristics
of the AD642 make it suitable for electrometer applications
such as photo diode preamplifiers and picoampere current-to-
voltage converters. The use of guarding techniques in printed
circuit board layout and construction is critical in printed circuit
board layout and construction is critical for achieving the
ultimate in low leakage performance that the AD642 can
deliver. The input guarding scheme shown in Figure 29 will
minimize leakage as much as possible; the guard ring should be
applied to both sides of the board. The guard ring is connected
to a low impedance potential at the same level as the inputs.
High impedance signal lines should not be extended for any
unnecessary length on a printed circuit; to minimize noise and
leakage, they must be carried in rigid shielded cables.
Figure 29. Board Layout for Guarding Inputs
Figure 28. Log-Ratio Amplifier
The conversion between current (or voltage) input and log
output is accomplished by the base emitter junctions of the dual
transistor Q1. Assuming Q1 has β>100, which is the case for the
specified transistor, the base-emitter voltage on side 1 is to a
close approximation:
V BE A = kT /q ln I1/IS1
This circuit is arranged to take the difference of the VBE’s of
Q1A and Q1B, thus producing an output voltage proportional
to the log of the ratio of the inputs:
V OUT
=
K
(V BE
A
V BE
B
)
=
KkT
q
(ln I1/IS1
ln I2/IS2 )
VOUT = K kT /q ln I1/I2
The scaling constant, K is set by R1 and RTC to about 16, to
produce 1 V change in output voltage per decade difference in
input signals. RTC is a special resistor with a +3500 ppm/°C
temperature coefficient, which makes K inversely proportional
to temperature, compensating for the “T” in kT/q. The log-ratio
transfer characteristic is therefore independent of temperature.
This particular log ratio circuit is free from the dynamic prob-
lems that plague many other log circuits. The –3 dB bandwidth
is 50 kHz over the top 3 decades, 100 nA to 100 µA, and
decreases smoothly at lower input levels. This circuit needs no
additional frequency compensation for stable operation from
input current sources, such as photodiodes, that may have
100 pF of shunt capacitance. For larger input capacitances a
20 pF integration capacitor around each amplifier will provide a
smoother frequency response.
INPUT PROTECTION
The AD642 is guaranteed for a maximum safe input potential
equal to the power supply potential. The input stage design also
allows differential input voltages of up to ± 0.5 volts while
maintaining the full differential input resistance of 1012 . This
makes the AD642 suitable for low speed voltage comparators
directly connected to a high impedance source.
Many instrumentation situations, such as flame detectors in gas
chromatographs, involve measurement of low level currents
from high-voltage sources. In such applications, a sensor fault
condition may apply a very high potential to the input of the
current-to-voltage converting amplifier. This possibility necessi-
tates some form of input protection. Many electrometer type
devices, especially CMOS designs, can require elaborate Zener
protection schemes which often compromise overall perfor-
mance. The AD642 requires input protection only if the source
is not current limited, and as such is similar to many JFET-
input designs. The failure mode would be overheating from
excess current rather than voltage breakdown. If the source is
not current-limited, all that is required is a resistor in series with
the affected input terminal so that the maximum overload
current is 1.0 mA (for example, 100 kfor a 100 volt overload).
This simple scheme will cause no significant reduction in
performance and give complete overload protection. Figure 30
shows proper connections.
The log ratio amplifier can be readily adjusted for optimum
accuracy by following this simple procedure. First, apply V1 =
–6–
Figure 30. AD642 Input Protection
REV. 0

6 Page







SeitenGesamt 6 Seiten
PDF Download[ AD642 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD640DC-Coupled Demodulating 120 MHz Logarithmic AmplifierAnalog Devices
Analog Devices
AD6402IF Transceiver SubsystemAnalog Devices
Analog Devices
AD641250 MHz Demodulating Logarithmic AmplifierAnalog Devices
Analog Devices
AD6411DECT RF TransceiverAnalog Devices
Analog Devices
AD642Precision/ Low Cost Dual BiFET Op AmpAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche