PDF AD6122 Data sheet ( Hoja de datos )

Número de pieza	AD6122
Descripción	CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator
Fabricantes	Analog Devices
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No Preview Available ! a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator Modulates IFs from 50 MHz to 350 MHz Integral Low Dropout Regulator Accepts 2.9 V to 4.2 V Input from Battery Low Power 10.4 mA at Midgain <10 ␮A Sleep Mode Operation Companion Receiver IF Chip Available (AD6121) APPLICATIONS CDMA, W-CDMA, AMPS and TACS Operation QPSK Transmitters GENERAL DESCRIPTION The AD6122 is a low power IF transmitter subsystem, specifi- cally designed for CDMA applications. It consists of an I and Q modulator, a divide-by-two quadrature generator, high dynamic range IF amplifiers with voltage-controlled gain and a power- down control input. An integral low dropout regulator allows operation from battery voltages from 2.9 V to 4.2 V. The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control with a nominal 75 dB/V scale factor. Either an internal or an external reference may be used to set the gain-control scale factor. The I and Q modulator accepts differential quadrature base- band inputs from a CDMA baseband converter. The local oscil- lator is injected at twice the IF frequency. A divide-by-two quadrature generator followed by dual polyphase filters ensures ± 1° quadrature accuracy. The modulator provides a common-mode reference output to bias the transmit DACs in the baseband converter to the same common-mode voltage as the modulator inputs, allowing dc coupling between the two ICs and thus eliminating the need to charge and discharge coupling capacitors. This allows the fastest power-up and power-down times for the AD6122 and CDMA baseband ICs. The AD6122 is fabricated using a 25 GHz ft silicon BiCMOS process and is packaged in a 28-lead SSOP and a 32-leadless LPCC chip scale package (5 mm × 5 mm). FUNCTIONAL BLOCK DIAGRAM VCC QUADRATURE MODULATOR OUTPUT I INPUT LOCAL OSCILLATOR INPUT QUADRATURE MODULATOR ،2 Q INPUT COMMON-MODE REFERENCE OUTPUT VPOS LOW VREG DROPOUT REGULATOR ATTENUATOR AD6122 GAIN CONTROL SCALE FACTOR IF AMPLIFIER INPUT IF AMPLIFIERS TRANSMIT OUTPUT TEMPERATURE COMPENSATION POWER- POWER- DOWN 1 DOWN 2 1.23 V REFERENCE GAIN CONTROL REFERENCE OUTPUT VOLTAGE INPUT GAIN CONTROL VOLTAGE INPUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page Test Figures MUST BE EQUAL LENGTHS I DATA 50⍀ MUST BE EQUAL LENGTHS Q DATA 50⍀ 0.1␮F +15V 8 1 X1 VP 2 X2 V–1 OUT 7 MODCMREF 3 Y1 A=1 4 Y2 V–1 AD830 VN 5 –15V 0.1␮F 0.1␮F +15V 8 1 X1 VP 2 X2 V–1 OUT 7 MODCMREF 3 Y1 A=1 4 Y2 V–1 AD830 VN 5 –15V 0.1␮F 0.1␮F +15V 8 1 X1 VP 2 X2 V–1 OUT 7 MODCMREF 3 Y1 A=1 4 Y2 V–1 AD830 VN 5 –15V 0.1␮F 0.1␮F +15V 8 1 X1 VP 2 X2 V–1 OUT 7 MODCMREF 3 Y1 A=1 4 Y2 V–1 AD830 VN 5 –15V 0.1␮F 50⍀ 50⍀ 50⍀ 50⍀ IIPP AD6122 IIPN QIPP MODOPP MODOPN QIPN LOIPP LOIPN VREG OUT 10nF 10nF 0.1␮F 450⍀ 205⍀ 450⍀ 0.1␮F VREG OUT MODCMREF LO INPUT AD6122 MOD_OUT Figure 1. Quadrature Modulator’s Characterization Input and Output Impedance Matches REV. B –5– 5 Page AD6122 VCC I INPUT LOCAL OSCILLATOR INPUT Q INPUT COMMON-MODE REFERENCE OUTPUT VPOS QUADRATURE MODULATOR OUTPUT QUADRATURE MODULATOR ATTENUATOR ،2 LOW DROPOUT REGULATOR VREG AD6122 GAIN CONTROL SCALE FACTOR IF AMPLIFIER INPUT IF AMPLIFIERS TRANSMIT OUTPUT TEMPERATURE COMPENSATION POWER- POWER- DOWN 1 DOWN 2 1.23 V REFERENCE OUTPUT GAIN CONTROL REFERENCE VOLTAGE INPUT GAIN CONTROL VOLTAGE INPUT Figure 21. Block Diagram THEORY OF OPERATION The CDMA Transmitter IF Subsystem (Figure 21) consists of an I and Q modulator with a divide-by-two quadrature genera- tor, high dynamic range IF amplifiers with voltage-controlled gain, a low dropout regulator and power-down control inputs. I and Q Modulator The I and Q modulator accepts differential quadrature baseband inputs from CDMA baseband converters. The LO is injected at twice the IF frequency. A divide-by-two quadrature generator followed by dual polyphase filters ensures ± 1° quadrature accu- racy (Figure 22). For 500 mV p-p differential I and Q input signals, the output power of the modulator will be –21 dBm referred to 1 kΩ when the output of the modulator is loaded with a 1 kΩ differential load. With the maximum input conditions stated above, the modulator outputs are a 225 µA p-p differential current; conse- quently, the output load will greatly affect the output power of the modulator. 2 ؋ IF LO INPUT 180؇ I ،2 I POLYPHASE FILTERS QUADRATURE OUTPUT TO MODULATOR Q ،2 Q Figure 22. Simplified Quadrature Generator Circuit The I and Q modulator also provides a common mode reference signal at the MODCMREF pin. This voltage is a dc voltage set to 1.408 V when a 2.7 V supply is used. It is used to dc bias the output of the DAC that provides I and Q inputs to the modulator. IF Amplifiers and Gain Control The IF amplifiers provide an 86 dB linear in dB gain control range. The input stage uses a differential, continuously variable attenuator based on Analog Devices’ patented X-AMP™ topol- ogy. This low noise attenuator consists of a differential R-2R ladder network, linear interpolator and a fixed gain amplifier. The IF amplifier’s input impedance is 1 kΩ differential. Similar to the I and Q modulator’s output, the IF amplifier’s output is a differential current, which will vary depending upon the gain control voltage. In order to achieve the specified gain, the out- put of the IF amplifiers should be loaded with a 1 kΩ differen- tial load. The gain control circuits contain both temperature compensa- tion circuitry and a choice of internal or external reference for adjusting the gain scale factor. The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control range with a nominal 75 dB/V scale factor. The external gain control input signal should be a clean signal. It is recommended to filter this signal in order to eliminate the noise that results from the DAC. If a noisy signal is used for the gain control voltage, VGAIN inband and adjacent channel noise peaking can occur at the output of the AD6122. A simple RC filter can be employed, but care should be taken with its design. If too big a resistor is used, a large voltage drop may occur across the resistor, resulting in lower gain than expected (as a result of a lower voltage reaching the AD6122). An RC filter with a 20 kHz bandwidth, employing a 1 kΩ resistor is appropri- ate. This results in an 8.2 nF capacitor. The resulting circuit is shown in Figure 23. Note that the input resistance at the VGAIN pin is approximately 100 kΩ. FROM BASEBAND CONVERTER 1k⍀ 8.2nF AD6122 VGAIN 109k⍀ X-AMP is a trademark of Analog Devices, Inc. REV. B –11– Figure 23. Gain Voltage Filtering 11 Page

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