PDF AD607 Data sheet ( Hoja de datos )

Número de pieza	AD607
Descripción	Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES Complete Receiver on a Chip: Monoceiver™ Mixer –15 dBm 1 dB Compression Point –8 dBm Input Third Order Intercept 500 MHz RF and LO Bandwidths Linear IF Amplifier Linear-in-dB Gain Control MGC or AGC with RSSI Output Quadrature Demodulator On-Board Phase-Locked Quadrature Oscillator Demodulates IFs from 400 kHz to 12 MHz Can Also Demodulate AM, CW, SSB Low Power 25 mW at 3 V CMOS Compatible Power-Down Interfaces to AD7013 and AD7015 Baseband Converters APPLICATIONS GSM, CDMA, TDMA, and TETRA Receivers Satellite Terminals Battery-Powered Communications Receivers Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem AD607 PIN CONFIGURATION 20-Lead SSOP (RS Suffix) FDIN 1 20 VPS1 COM1 2 19 FLTR PRUP 3 18 IOUT LOIP 4 17 QOUT RFLO 5 AD607 16 VPS2 RFHI 6 TOP VIEW (Not to Scale) 15 DMIP GREF 7 14 IFOP MXOP 8 13 COM2 VMID 9 12 GAIN/RS IFHI 10 11 IFLO GENERAL DESCRIPTION The AD607 is a 3 V low power receiver IF subsystem for opera- tion at input frequencies as high as 500 MHz and IFs from 400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and Q demodulators, a phase-locked quadrature oscillator, AGC detector, and a biasing system with external power-down. The AD607’s low noise, high intercept mixer is a doubly- balanced Gilbert cell type. It has a nominal –15 dBm input referred 1 dB compression point and a –8 dBm input referred third-order intercept. The mixer section of the AD607 also includes a local oscillator (LO) preamplifier, which lowers the required LO drive to –16 dBm. The gain control input can serve as either a manual gain control (MGC) input or an automatic gain control (AGC) voltage- based RSSI output. In MGC operation, the AD607 accepts an external gain-control voltage input from an external AGC detec- tor or a DAC. In AGC operation, an onboard detector and an external averaging capacitor form an AGC loop that holds the IF output level at ± 300 mV. The voltage across this capacitor then provides an RSSI output. The I and Q demodulators provide inphase and quadrature baseband outputs to interface with Analog Devices’ AD7013 (IS54, TETRA, MSAT) and AD7015 (GSM) baseband con- verters. A quadrature VCO phase-locked to the IF drives the I and Q demodulators. The I and Q demodulators can also de- modulate AM; when the AD607’s quadrature VCO is phase locked to the received signal, the in-phase demodulator becomes a synchronous product detector for AM. The VCO can also be phase-locked to an external beat-frequency oscillator (BFO), and the demodulator serves as a product detector for CW or SSB reception. Finally, the AD607 can be used to demodulate BPSK using an external Costas Loop for carrier recovery. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page Typical Performance Characteristics–AD607 HP8656B IEEE RF_OUT SYNTHESIZER HP8656B IEEE RF_OUT SYNTHESIZER HP8656B IEEE RF_OUT SYNTHESIZER HP6633A VPOS IEEE VNEG SPOS SNEG DCPS HP34401A CPIB DMM HI LO I DP8200 IEEE VREF VPOS VNEG SPOS SNEG 50Ω 50Ω HP8764B 0 1 0 S0 S1 1V CHARACTERIZATION BOARD RFHI LOIP RX L MXOP R5 1kΩ 0 HP8765B 1C S0 V S1 IFHI DMIP FDIN PLL IFOP IOUT P6205 TEK1105 X10 OUT IN1 OUT1 FET PROBE IN2 OUT2 PROBE SUPPLY QOUT VPOS PRUP GAIN BIAS Figure 1. Mixer/Amplifier Test Set 50Ω 50Ω HP8764B 0 1 0 S0 S1 1 V HP8765B 0 1C S0 V S1 HP8594E RF_IN IEEE SPEC AN HP8720C PORT_1 IEEE_488 PORT_2 NETWORK AN HP346B 28V NOISE NOISE SOURCE HP8656B IEEE RF_OUT SYNTHESIZER 0 HP8765B 1C S0 V S1 HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VREF VNEG SPOS SNEG CHARACTERIZATION BOARD RFHI RX L MXOP LOIP IFHI IFOP HP8765B 0 C1 S1 V S0 50Ω HP8970A RF_IN 28V_OUT NOISE FIGURE METER DMIP FDIN PLL IOUT QOUT VPOS PRUP GAIN BIAS Figure 2. Mixer Noise Figure Test Set REV. 0 –5– 5 Page 80 70 60 50 40 30 20 10 0 –10 0.1 VGAIN = 0.3V VGAIN = 0.6V VGAIN = 1.2V VGAIN = 1.8V VGAIN = 2.4V 1 10 INTERMEDIATE FREQUENCY – MHz 100 Figure 19. IF Amplifier Gain vs. Frequency, T = +25°C, VPOS = 3 V, VREF = 1.5 V AD607 –90.00 –100.00 –110.00 –120.00 –130.00 –140.00 –150.00 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 CARRIER FREQUENCY OFFSET, f(fm) – Hz 1.00E+07 Figure 22. PLL Phase Noise L (F) vs. Frequency, VPOS = 3 V, C3 = 0.1 µF, IF = 10.7 MHz 10 8 6 IF AMP 4 2 0 –2 MIXER –4 –6 –8 –10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 GAIN VOLTAGE – Volts Figure 20. AD607 Gain Error vs. Gain Control Voltage, Representative Part 996.200 µs 1.00870 ms 1.02120 ms Timebase = 2.5 µs/div Memory 1 = 100.0 mVolts/div Timebase = 2.50 µs/div Memory 2 = 20.00 mVolts/div Timebase = 2.50 µs/div Delta T = 16.5199 µs Start = 1.00048 ms Delay = 1.00870 ms Offset = 127.3 mVolts Delay = 1.00870 ms Offset = 155.2 mVolts Delay = 1.00870 ms Stop = 1.01700 ms Trigger on External at Pos. Edge at 134.0 mVolts Figure 21. PLL Acquisition Time 2.5 2 1.5 0.1 1 10 PLL FREQUENCY – MHz 100 Figure 23. PLL Loop Voltage at FLTR (KVCO) vs. Frequency 8 7 6 5 4 3 2 1 0 85 86 87 88 89 90 91 92 93 94 95 QUADRATURE ANGLE – Degrees Figure 24. Demodulator Quadrature Angle, Histogram, T = +25°C, VPOS = 3 V, IF = 10.7 MHz REV. 0 –11– 11 Page

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