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AD606 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD606
Beschreibung 80 dB Demodulating Logarithmic Amplifier
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 13 Seiten
AD606 Datasheet, Funktion
a 50 MHz, 80 dB Demodulating
Logarithmic Amplifier with Limiter Output
AD606
FEATURES
Logarithmic Amplifier Performance
–75 dBm to +5 dBm Dynamic Range
1.5 nV/Hz Input Noise
Usable to >50 MHz
37.5 mV/dB Voltage Output
On-Chip Low-Pass Output Filter
Limiter Performance
؎1 dB Output Flatness over 80 dB Range
؎3؇ Phase Stability at 10.7 MHz over 80 dB Range
Adjustable Output Amplitude
Low Power
+5 V Single Supply Operation
65 mW Typical Power Consumption
CMOS-Compatible Power-Down to 325 W typ
<5 s Enable/Disable Time
APPLICATIONS
Ultrasound and Sonar Processing
Phase-Stable Limiting Amplifier to 100 MHz
Received Signal Strength Indicator (RSSI)
Wide Range Signal and Power Measurement
PRODUCT DESCRIPTION
The AD606 is a complete, monolithic logarithmic amplifier
using a 9-stage “successive-detection” technique. It provides
both logarithmic and limited outputs. The logarithmic output is
from a three-pole post-demodulation low-pass filter and provides
a loadable output voltage of +0.1 V dc to +4 V dc. The logarith-
mic scaling is such that the output is +0.5 V for a sinusoidal
input of –75 dBm and +3.5 V at an input of +5 dBm; over this
range the logarithmic linearity is typically within ± 0.4 dB. All
scaling parameters are proportional to the supply voltage.
The AD606 can operate above and below these limits, with
reduced linearity, to provide as much as 90 dB of conversion
range. A second low-pass filter automatically nulls the input
offset of the first stage down to the submicrovolt level. Adding
external capacitors to both filters allows operation at input fre-
quencies as low as a few hertz.
The AD606’s limiter output provides a hard-limited signal
output as a differential current of ± 1.2 mA from open-collector
outputs. In a typical application, both of these outputs are
loaded by 200 resistors to provide a voltage gain of more than
90 dB from the input. Transition times are 1.5 ns, and the
phase is stable to within ± 3° at 10.7 MHz for signals from
–75 dBm to +5 dBm.
The logarithmic amplifier operates from a single +5 V supply
and typically consumes 65 mW. It is enabled by a CMOS logic
level voltage input, with a response time of <5 µs. When dis-
abled, the standby power is reduced to <1 mW within 5 µs.
The AD606J is specified for the commercial temperature range
of 0°C to +70°C and is available in 16-lead plastic DIPs or
SOICs. Consult the factory for other packages and temperature
ranges.
FUNCTIONAL BLOCK DIAGRAM
INHI
16
COMM
15
PRUP
14
VPOS
13
FIL1
12
FIL2
11
LADJ
10
LMHI
9
REFERENCE
AND POWER-UP
30k
30k
30pF
360k
X1
30pF
360k
OFFSET-NULL
LOW-PASS FILTER
1.5k
250
1.5k
HIGH-END
DETECTORS
AD606
MAIN SIGNAL PATH
11.15dB/STAGE
12A/dB
ONE-POLE
FILTER
2A/dB
9.375k
9.375k
2pF TWO-POLE
SALLEN-KEY
FILTER
X2
2pF
FINAL
LIMITER
REV. B
1
INLO
2
COMM
3
ISUM
4
ILOG
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
5
BFIN
6
VLOG
7
OPCM
8
LMLO
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






AD606 Datasheet, Funktion
AD606
for that converter should be a fractional part of VPOS, if possible.
The slope is essentially independent of temperature.
The intercept PX is essentially independent of either the supply
voltage or temperature. However, the AD606 is not factory
calibrated, and both the slope and intercept may need to be
externally adjusted. Following calibration, the conformance to
an ideal logarithmic law will be found to be very close, particu-
larly at moderate frequencies (see Figure 14), and still accept-
able at the upper end of the frequency range (Figure 15).
CIRCUIT DESCRIPTION
Figure 2 is a block diagram of the AD606, which is a complete
logarithmic amplifier system in monolithic form. It uses a total
of nine limiting amplifiers in a “successive detection” scheme to
closely approximate a logarithmic response over a total dynamic
range of 90 dB (Figure 2). The signal input is differential, at
nodes INHI and INLO, and will usually be sinusoidal and ac
coupled. The source may be either differential or single-sided;
the input impedance is about 2.5 kin parallel with 2 pF. Seven
of the amplifier/detector stages handle inputs from –80 dBm
(32 µV rms) up to about –14 dBm (45 mV rms). The noise floor
is about –83 dBm (18 µV rms). Another two stages receive the
input attenuated by 22.3 dB, and respond to inputs up to
+10 dBm (707 mV rms). The gain of each of these stages is
11.15 dB and is accurately stabilized over temperature by a
precise biasing system.
The detectors provide full-wave rectification of the alternating
signal present at each limiter output. Their outputs are in the
form of currents, proportional to the supply voltage. Each cell
incorporates a low-pass filter pole, as the first step in recovering
the average value of the demodulated signal, which contains
appreciable energy at even harmonics of the input frequency. A
further real pole can be introduced by adding a capacitor be-
tween the summing node ISUM and VPOS. The summed de-
tector output currents are applied to a 6:1 reduction current
mirror. Its output at ILOG is scaled 2 µA/dB, and is converted
to voltage by an internal load resistor of 9.375 kbetween
ILOG and OPCM (output common, which is usually grounded).
The nominal slope at this point is 18.75 mV/dB (375 mV/
decade).
In applications where VLOG is taken to an A/D converter which
allows the use of an external reference, this reference input
should also be connected to the same +5 V supply. The power
supply voltage may be in the range +4.5 V to +5.5 V, providing
a range of slopes from nominally 33.75 mV/dB (675 mV/ de-
cade) to 41.25 mV/dB (825 mV/decade).
A buffer amplifier, having a gain of two, provides a final output
scaling at VLOG of 37.5 mV/dB (750 mV/decade). This low-
impedance output can run from close to ground to over +4 V
(using the recommended +5 V supply) and is tolerant of resis-
tive and capacitive loads. Further filtering is provided by a con-
jugate pole pair, formed by internal capacitors which are an
integral part of the output buffer. The corner frequency of the
overall filter is 2 MHz, and the 10%–90% rise time is 150 ns.
Later, we will show how the slope and intercept can be altered
using simple external adjustments. The direct buffer input
BFIN is used in these cases.
The last limiter output is available as complementary currents
from open collectors at pins LMHI and LMLO. These currents
are each 1.2 mA typical with LADJ grounded and may be con-
verted to voltages using external load resistors connected to
VPOS; typically, a 200 resistor is used on just one output.
The voltage gain is then over 90 dB, resulting in a hard-limited
output for all input levels down to the noise floor. The phasing
is such that the voltage at LMHI goes high when the input
(INHI to INLO) is positive. The overall delay time from the
signal inputs to the limiter outputs is 8 ns. Of particular impor-
tance is the phase stability of these outputs versus input level. At
50 MHz, the phase typically remains within ± 4° from –70 dBm
to +5 dBm. The rise time of this output (essentially a square
wave) is about 1.2 ns, resulting in clean operation to more than
70 MHz.
INHI
16
COMM
15
PRUP
14
VPOS
13
FIL1
12
FIL2
11
LADJ
10
REFERENCE
AND POWER-UP
30k
30k
30pF
360k
X1
30pF
360k
OFFSET-NULL
LOW-PASS FILTER
LMHI
9
REV. B
1.5k
250
1.5k
HIGH-END
DETECTORS
AD606
MAIN SIGNAL PATH
11.15dB/STAGE
12A/dB
ONE-POLE
FILTER
2A/dB
9.375k
9.375k
2pF TWO-POLE
SALLEN-KEY
FILTER
X2
2pF
FINAL
LIMITER
1
INLO
2
COMM
3
ISUM
4
ILOG
5
BFIN
6
VLOG
7
OPCM
8
LMLO
Figure 2. Simplified Block Diagram
–5–

6 Page









AD606 pdf, datenblatt
AD606
Figure 19. VLOG Output for a Pulsed
10.7 MHz Input; Top Trace: –35 dBm
to +5 dBm; Middle Trace: –15 dBm to
–55 dBm; Bottom Trace: –35 dBm to –
75 dBm
Figure 20. Example of Test Signal
Used for Figure 19
Figure 21. VLOG Output for 10.7 MHz
CW Input with PRUP Toggled ON
and OFF; Top Trace: +5 dBm Input;
Middle Trace: –35 dBm Input; Bottom
Trace: –75 dBm; PRUP Input from
HP8112A: 0 to 4 V, 10 µs Pulsewidth
with 10 kHz Repetition Rate
+5V
0.1F
FLUKE 6082A
SYNTHESIZED
SIGNAL
GENERATOR
MODULATED
PULSE
TESTS
–10dB TO +30dB
(10.7MHz SWEPT
GAIN TESTS ONLY)
AD602
SWEPT GAIN
TESTS
HEWLETT PACKARD
8112A PULSE
GENERATOR
RF C1
INPUT 100pF
C3
150pF
51.1
AD606JN
NC NC NC
C2
100pF
NC = NO CONNECT
200
+5V
200
TEKTRONIX 7704A
MAINFRAME
OSCILLOSCOPE
10 x P6201 7A18 7B53A
ATTN PROBES AMP TIME-BASE
6137 7A24
PROBES AMP
Figure 22. Test Setup for Characterization Data
REV. B
–11–

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