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AD7667 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7667
Beschreibung 16-Bit 1 MSPS SAR Unipolar ADC with Ref
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 23 Seiten
AD7667 Datasheet, Funktion
PRELIMINARY TECHNICAL DATA
a 16-Bit 1 MSPS SAR Unipolar ADC with Ref
Preliminary Technical Data
AD7667*
FEATURES
Throughput:
1 MSPS (Warp Mode)
800 kSPS (Normal Mode)
INL: ±2.5 LSB Max (±0.0038% of Full Scale)
16 Bits Resolution with No Missing Codes
Analog Input Voltage Range: 0 V to 2.5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPITM/QSPITM/MICROWIRETM/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
112 mW Typ without REF, 122 mW Typ with REF
15 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP);
48-Lead Chip Scale Package (LFCSP);
Pin-to-Pin Compatible with PulSAR ADCs
APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
FUNCTIONAL BLOCK DIAGRAM
AGND
AVDD
IN
INGND
PDREF
PDBUF
PD
RESET
REFBUFIN REF REFGND
2.5 V REF
AD7667
SWITCHED
CAP DAC
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
WARP IMPULSE CNVST
DVDD DGND
SERIAL
PORT
16
PARALLEL
INTERFACE
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP
Type / kSPS
Pseudo
Differential
True Bipolar
True
Differential
PulSAR Selection
100 - 250
AD7651
AD7660/61
AD7663
AD7675
500 - 570
AD7650/52
AD7664/66
AD7665
AD7676
1000
AD7653
AD7667
AD7671
AD7677
GENERAL DESCRIPTION
The AD7667 is a 16-bit, 1 MSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high-speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports.
It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode
(Normal) and, for low power applications, a reduced power
mode (Impulse) where the power is scaled with the through-
put.
It is fabricated using Analog Devices’ high-performance, 0.6 micron
CMOS process, with correspondingly low cost and is available in a
48-lead LQFP and a tiny 48-lead LFCSP with operation speci-
fied from –40°C to +85°C.
*Patent pending.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE ia a trademark of National Semiconductor Corporation
REV. PrA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7667 is a 1 MSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Internal Reference
The AD7667 has an internal reference and allows for an
external reference to be used.
3. Superior INL
The AD7667 has a maximum integral nonlinearity of 2.5
LSB with no missing 16-bit code.
4. Single-Supply Operation
The AD7667 operates from a single 5 V supply and dissipates
a typical of 112 mW. In impulse mode, its power dissi-
pation decreases with the throughput. It consumes 7 µW
maximum when in power-down.
5. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement
compatible with both 3 V or 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






AD7667 Datasheet, Funktion
AD7667
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION
48-Lead LQFP
(ST-48)
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1
AVDD 2
NC 3
BYTESWAP 4
OB/2C 5
WARP 6
IMPULSE 7
SER/PAR 8
D0 9
D1 10
D2/SCLK0 11
D3/SCLK1 12
PIN 1
IDENTIFIER
AD7667
TOP VIEW
(Not to Scale)
36 AGND
35 CNVST
34 PD
33 RESET
32 CS
31 RD
30 DGND
29 BUSY
28 D15
27 D14
26 D13
25 D12
NC = NO CONNECT
13 14 15 16 17 18 19 20 21 22 23 24
Pin No. Mnemonic
1
2
3, 40–42,
44
4
AGND
AVDD
NC
BYTESWAP
Type
P
P
DI
5
OB/2C
DI
6
WARP
DI
7 IMPULSE DI
8
SER/PAR
DI
9,10 DATA[0:1] DI
11,12 DATA[2:3]or DI/O
DIVSCLK[0:1]
13
DATA[4]
DI/O
or EXT/INT
14
DATA[5]
DI/O
or INVSYNC
PIN FUNCTION DESCRIPTIONS
Description
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the
MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB
is output on D[7:0].
Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these
outputs are in high impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
Data Output Bus. When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is
LOW, which is serial master read after convert, these inputs, part of the serial port, are
used to slow down if desired the internal serial clock which clocks the data output. In
other serial moes, these pins are not used
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is syn
chronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active
–6– REV. PrA

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AD7667 pdf, datenblatt
AD7667
PRELIMINARY TECHNICAL DATA
CIRCUIT INFORMATION
The AD7667 is a very fast, low power, single supply, pre-
cise 16-bit analog-to-digital converter (ADC). The
AD7667 features different modes to optimize performances
according to the applications.
In warp mode, the AD7667 is capable of converting
1,000,000 samples per second (1MSPS).
The AD7667 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7667 can be operated from a single 5 V supply and
be interfaced to either 5 V or 3 V digital logic. It is housed
in either a 48-lead LQFP package or a 48-lead LFCSP that
saves space and allows flexible configurations as either serial or
parallel interface. The AD7667 is a pin-to-pin compatible
upgrade of the AD7661/64/66.
CONVERTER OPERATION
The AD7667 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected to a
“dummy” capacitor of the same value as the capacitive DAC
array.
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the CNVST input goes low, a conversion phase is initi-
ated. When the conversion phase begins, SWA and SWB are
opened first. The capacitor array and the “dummy” capacitor are
then disconnected from the inputs and connected to the REF-
GND input. Therefore, the differential voltage between IN and
INGND captured at the end of the acquisition phase is applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between REFGND or REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4, . . . VREF/65536).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings BUSY output low.
Modes of Operation
The AD7667 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 1
MSPS. However, in this mode, and this mode only, the full
specified accuracy is guaranteed only when the time between
conversion does not exceed 1 ms. If the time between two con-
secutive conversions is longer than 1 ms, for instance, after
power-up, the first conversion result should be ignored. This
mode makes the AD7667 ideal for applications where both high
accuracy and fast sample rate are required.
The normal mode is the fastest mode (800 kSPS) without any
limitation about the time between conversions. This mode
makes the AD7667 ideal for asynchronous applications such as
data acquisition systems, where both high accuracy and fast
sample rate are required.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 15 µW. This feature
makes the AD7667 ideal for battery-powered applications.
Transfer Functions
Using the OB/2C digital input, the AD7667 offers two output
codings: straight binary and two’s complement. The LSB size is
VREF/65536, which is about 38.15 µV. The ideal transfer charac-
teristic for the AD7667 is shown in Figure 4 and Table I.
111...111
111...110
111...101
1 LSB = VREF/65536
000...010
000...001
000...000
0V
1 LSB
0.5 LSB
VREF › 1 LSB
VREF › 1.5 LSB
ANALOG INPUT
Figure 4. ADC Ideal Transfer Function
IN
REF
REFGND
INGND
MSB
LSB SWA
SWITCHES
CONTROL
32,768C 16,384C
4C 2C
CC
65,536C
COMP
SWB
CONTROL
LOGIC
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
–12–
REV. PrA

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