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PDF AD7661 Data sheet ( Hoja de datos )
| Número de pieza | AD7661 | |
| Descripción | 16-Bit 1 MSPS SAR Unipolar ADC with Ref | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
2.5 V internal reference: typical drift 3 ppm/°C
Guaranteed max drift 15 ppm/°C
Throughput: 100 kSPS
INL: ±2.5 LSB max (±0.0038% of full scale)
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
Both AC and DC specifications
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPITM/MICROWIRETM/DSP compatible
Single 5 V supply operation
Power dissipation
16 mW typ, 160 µW @ 1 kSPS without REF
40 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Medical instruments
Digital signal processing
Spectrum analysis
Instrumentation
Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7661* is a 16-bit, 100 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports. The AD7661 is hardware factory-calibrated and
comprehensively tested to ensure ac parameters such as signal-
to-noise ratio (SNR) and total harmonic distortion (THD), in
addition to the more traditional dc parameters of gain, offset,
and linearity.
The AD7661 is available in a 48-lead LQFP and a tiny 48-lead
LFCSP with operation specified from –40°C to +85°C.
*Patent Pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
16-Bit 100 kSPS PulSAR®
Unipolar ADC with Reference
AD7661
FUNCTIONAL BLOCK DIAGRAM
REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN
INGND
PDREF
PDBUF
PD
RESET
AD7661
REF
SWITCHED
CAP DAC
SERIAL
PORT
16
CLOCK
PARALLEL
INTERFACE
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CNVST
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
BYTESWAP
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
Type/kSPS
Pseudo-
Differential
True Bipolar
True
Differential
18-Bit
Multichannel/
Simultaneous
100–250
AD7651
AD7660/AD7661
AD7663
AD7675
AD7678
500–570
AD7650/AD7652
AD7664/AD7666
AD7665
AD7676
AD7679
AD7654
AD7655
800–
1000
AD7653
AD7667
AD7671
AD7677
AD7674
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7661 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL.
The AD7661 has a maximum integral nonlinearity of
2.5 LSB with no missing 16-bit codes.
3. Internal Reference.
The AD7661 has an internal reference with a typical
temperature drift of 3 ppm/°C.
4. Single-Supply Operation.
The AD7661 operates from a single 5 V supply. Its power
dissipation decreases with throughput.
5. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD7661
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter
Symbol Min
Refer to Figure 33 and Figure 34
Convert Pulse Width
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulse Width
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay1
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period2
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t1 10
t2 10
t3
t4
t5
t6 10
t7
t8 8.75
t9 10
t10
t11 12
t12
t13 5
t14
t15
t16
t17
t18 3
t19 25
t20 12
t21 7
t22 4
t23 2
t24 3
t25
t26
t27
t28
t29
t30
t31 5
t32 3
t33 5
t34 5
t35 25
t36 10
t37 10
Typ
2
525
See Table 4
1.25
25
Max
35
1.25
1.25
1.25
45
15
10
10
10
40
10
10
10
18
Unit
ns
µs
ns
µs
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Rev. 0 | Page 5 of 28
5 Page 
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error
The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
Unipolar Zero Error
The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number Of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) and is expressed in bits by the
following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
AD7661
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the AD7661 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Overvoltage Recovery
Overvoltage recovery is the time required for the ADC to
recover to full accuracy after an analog input signal 150% of the
full-scale value is reduced to 50% of the full-scale value.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the
maximum and minimum reference output voltage (VREF)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C
using the following equation:
TCVREF
(
ppm /
°C)
=
VREF ( Max)
VREF (25°C) ×
– VREF
(TMAX
( Min)
– TMIN
)
×106
where:
VREF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX
VREF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX
VREF(25°C) = VREF at +25°C
TMAX = +85°C
TMIN = –40°C
Thermal Hysteresis
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
T_HYS– = +25°C to TMIN to +25°C
It is expressed in ppm using the following equation:
VHYS ( ppm) =
VREF (25°C) − VREF (T _ HYS)
VREF (25°C)
× 106
where:
VREF(25°C) = VREF at 25°C
VREF(T_HYS) = Maximum change of VREF at T_HYS+ or
T_HYS–.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7661.PDF ] | |
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