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PDF AD7660 Data sheet ( Hoja de datos )
| Número de pieza | AD7660 | |
| Descripción | 16-Bit/ 100 kSPS CMOS ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Throughput: 100 kSPS
INL: ؎3 LSB Max (؎0.0046% of Full-Scale)
16 Bits Resolution with No Missing Codes
S/(N+D): 87 dB Min, 90 dB Typ @ 10 kHz
THD: –96 dB Max @ 10 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
Single 5 V Supply Operation
21 mW Typical Power Dissipation, 21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
Pin-to-Pin Compatible with the AD7664
APPLICATIONS
Data Acquisition
Battery-Powered Systems
PCMCIA
Instrumentation
Automatic Test Equipment
Scanners
Medical Instruments
Process Control
16-Bit, 100 kSPS CMOS ADC
AD7660*
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND
DVDD DGND
IN
INGND
AD7660
SWITCHED
CAP DAC
SERIAL
PORT
16
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
PARALLEL
INTERFACE
OVDD
OGND
DATA[15:0]
BUSY
RD
CS
SER/PAR
OB/2C
CNVST
GENERAL DESCRIPTION
The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains an internal conversion clock, error cor-
rection circuits, and both serial and parallel system interface ports.
The AD7660 is hardware factory calibrated and is comprehensively
tested to ensure such ac parameters as signal-to-noise ratio (SNR)
and total harmonic distortion (THD), in addition to the more
traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high-performance, 0.6
micron CMOS process with correspondingly low cost, and is
available in a 48-lead LQFP with operation specified from
–40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7660 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL
The AD7660 has a maximum integral nonlinearity of 3 LSBs
with no missing 16-bit code.
3. Single-Supply Operation
The AD7660 operates from a single 5 V supply and only
dissipates 21 mW typical. Its power dissipation decreases
with the throughput to, for instance, only 21 µW at a 100 SPS
throughput. It consumes 7 µW maximum when in power-down.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
*Patent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
Pin
No.
1
2
3, 6, 7,
40–48
4
5
8
9–12
13
14
15
16
17
18
19
20
21
PIN FUNCTION DESCRIPTIONS
AD7660
Mnemonic
AGND
AVDD
NC
Type
P
P
Description
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
No Connect.
DGND
OB/2C
DI
DI
SER/PAR
DI
DATA[0:3] DO
DATA[4]
DI/O
or EXT/INT
DATA[5]
DI/O
or INVSYNC
DATA[6]
DI/O
or INVSCLK
DATA[7]
DI/O
or RDC/SDIN
OGND
OVDD
DVDD
DGND
DATA[8]
or SDOUT
P
P
P
P
DO
Must be tied to digital ground.
Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless
of the state of SER/PAR.
When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is syn-
chronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state
of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-
nal. It is active in both master and slave mode.
When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the con-
version results from two or more ADCs onto a single SDOUT line. The digital data level on
SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data is output on SDOUT only when the conversion is complete.
Input/Output interface Digital Power Ground.
Input/Output interface Digital Power. Nominally at the same supply than the supply of the
host interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground.
When SER/PAR is LOW, this output is used as the Bit 8 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is
valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next
rising edge.
REV. 0
–5–
5 Page 
AD7660
IN
REF
REFGND
INGND
MSB
LSB LSB SWA
SWITCHES
CONTROL
32768C 16384C
4C 2C
CC
BUSY
67536C
COMP
SWB
CONTROL
LOGIC
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7660 is a fast, low-power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7660 is capable of
converting 100,000 samples per second (100 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 21 µW. This feature
makes the AD7660 ideal for battery-powered applications.
The AD7660 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7660 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and allows
flexible configurations as either serial or parallel interface. The
AD7660 is pin-to-pin-compatible with the AD7664.
CONVERTER OPERATION
The AD7660 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected
to a “dummy” capacitor of the same value as the capacitive
DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete and the CNVST input
goes or is low, a conversion phase is initiated. When the conver-
sion phase begins, SWA and SWB are opened first. The capacitor
array and the “dummy” capacitor are then disconnected from
the inputs and connected to the REFGND input. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs, caus-
ing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the comple-
tion of this process, the control logic generates the ADC output
code and brings BUSY output low.
111...111
111...110
111...101
1 LSB = VREF/65536
000...010
000...001
000...000
0V 1 LSB
0.5 LSB
VREF –1 LSB
VREF –1.5 LSB
ANALOG INPUT
Figure 4. ADC Ideal Transfer Function
Transfer Functions
Using the OB/2C digital input, the AD7660 offers two output
codings: straight binary and two’s complement. The LSB size is
VREF/65536, which is about 38.15 µV. The ideal transfer charac-
teristic for the AD7660 is shown in Figure 4 and Table I.
Table I. Output Codes and Ideal Input Voltages
Description
Analog
Input
Digital Output Code
(Hexa)
Straight Two’s
Binary Complement
FSR – 1 LSB
FSR – 2 LSB
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
2.499962 V
2.499923 V
1.250038 V
1.25 V
1.249962 V
38 µV
0V
FFFF1
FFFE
8001
8000
7FFF
0001
00002
7FFF1
7FFE
0001
0000
FFFF
8001
80002
NOTES
1This is also the code for overrange analog input (VIN – VINGND above
VREF – VREFGND).
2This is also the code for underrange analog input (VIN below VINGND).
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD7660.PDF ] | |
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