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AD760 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD760
Beschreibung 16/18-Bit Self-Calibrating Serial/Byte DACPORT
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
AD760 Datasheet, Funktion
a
16/18-Bit Self-Calibrating
Serial/Byte DACPORT
AD760
FEATURES
±0.2 LSB (±0.00031%) Typ Peak DNL and INL
±0.5 LSB (±0.00076%) Typ Unipolar Offset, Bipolar Zero
17-Bit Monotonicity Guaranteed
18-Bit Resolution (in Serial Mode)
Complete 16/18-Bit D/A Function
On-Chip Output Amplifier
On-Chip Buried Zener Voltage Reference
Microprocessor Compatible
Serial or Byte Input
Double Buffered Latches
Asynchronous Clear Function
Serial Output Pin Facilitates Daisy Chaining
Pin Strappable Unipolar or Bipolar Output
Low THD+N: 0.005%
MUX Output Control on Power-Up and Supply Glitches
PRODUCT DESCRIPTION
The AD760 is a complete 16/18-bit self-calibrating monolithic
DAC (DACPORT®) with onboard voltage reference, double
buffered latches and output amplifier. It is manufactured on
Analog Devices’ BiMOS II process. This process allows the fab-
rication of low power CMOS logic functions on the same chip
as high precision bipolar linear circuitry.
Self-calibration is initiated by simply pulsing the CAL pin low.
The CALOK pin indicates when calibration has been success-
fully completed. The output multiplexer (MUXOUT) can be used
to send the output to the bottom of the output range during
calibration.
Data can be loaded into the AD760 as straight binary, serial
data or as two 8-bit bytes. In serial mode, 16-bit or 18-bit data
can be used and the serial mode input format is pin selectable,
to be MSB or LSB first. This is made possible by three digital
input pins which have dual functions (Pins 12, 13, and 14). In
byte mode the user can similarly define whether the high byte or
low byte is loaded first. The serial output (SOUT) pin allows the
user to daisy chain several AD760s by shifting the data through
the input latch into the next DAC thus minimizing the number
of control lines required in a multiple DAC application. The
double buffered latch structure eliminates data skew errors and
provides for simultaneous updating of DACs in a multi-DAC
system.
The asynchronous CLR function can be configured to clear the
output to minus full-scale or midscale depending on the state of
Pin 17 when CLR is strobed. The AD760 also powers up with the
FUNCTIONAL BLOCK DIAGRAM
UNI/
BIP CLR 17
OR LBE
HBE 18
SER 19
CLR 20
LDAC 21
REF IN 25
MSB/ 18/16
SIN LSB SERIAL
OR OR OR
CS DB0 DB1 DB2
DB7
16 14 13 12
7
AD760
16/18-BIT
INPUT REGISTER
10k
16/18-BIT DAC LATCH
10k
9.95k
MAIN DAC
RAM
REF OUT 26 +10V
REF
CALIBRATION DAC
15 SOUT
24 SPAN/
BIP
OFF
23 VOUT
27 MUXOUT
28 MUXIN
22 AGND
CALIBRATION SEQUENCER
1
CALOK
2
CAL
3
–VEE
4
+VCC
5
+VLL
6
DGND
MUX output in a predetermined state by means of a digital and
analog power supply detection circuit. This is particularly use-
ful for robotic and industrial control applications.
The AD760 is available in a 28-pin, 600 mil cerdip package.
The AQ version is specified from –40°C to +85°C.
0.75
VOUT = –10V TO +10V
RL = 2k
CL = 1000pF
0.25
0
–0.25
–0.75
0
16384
32768
49152
INPUT CODE – Decimal
Typical Integral Nonlinearity
65535
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DACPORT is a registered trademark of Analog Devices, Inc.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






AD760 Datasheet, Funktion
AD760
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS – 1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be greater than or equal to –1 LSB over the temperature
range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD760 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at TMIN, 25°C and TMAX and dividing
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%). THD+N is a
measure of the magnitude and distribution of linearity error, dif-
ferential linearity error, quantization error and noise. The distri-
bution of these errors may be different, depending upon the
amplitude of the output signal. Therefore, to be the most useful,
THD+N should be specified for both large and small signal am-
plitudes.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is
defined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many as
possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the VOUT pin. This noise is digital feedthrough.
THEORY OF OPERATION
The AD760 uses autocalibration circuitry to produce a true
16-bit DAC with typically 0.2 LSB Integral and Differential
Linearity Error and 0.5 LSB Offset Error. The block diagram
in Figure 2 shows the circuit components needed for calibration.
The MAIN DAC uses an array of bipolar current sources with
MOS current steering switches to develop a current propor-
tional to the applied digital word, ranging from 0 mA to 2 mA.
A segmented architecture is used, where the most significant
four data bits are thermometer decoded to drive 15 equal cur-
rent sources. The lesser bits are scaled using an R-2R ladder,
then applied together with the segmented sources to the sum-
ming node of the output amplifier. An extra LSB is included in
the MAIN DAC, for use during calibration.
The self-calibration architecture of the AD760 attempts to
reduce the linearity errors of its transfer function. The algorithm
first checks for bipolar or unipolar operation, calibrates either
bipolar zero or unipolar offset, and then removes the carry er-
rors (DNL errors) associated with the upper 6 bits (64 codes).
Once calibrated, the top six bits of a code entering the MAIN
DAC simultaneously address the RAM, calling up a correction
code that is then applied to the CALDAC. The output cur-
rents of both the MAIN DAC and CALDAC are combined in
the summing amplifier to produce the corrected output voltage.
UNI/
BIP CLR 17
OR LBE
HBE 18
SER 19
CLR 20
LDAC 21
REF IN 25
MSB/ 18/16
SIN LSB SERIAL
OR OR OR
CS DB0 DB1 DB2
DB7
16 14 13 12
7
16/18-BIT
INPUT REGISTER
AD760
10k
16/18-BIT DAC LATCH
10k
9.95k
MAIN DAC
RAM
REF OUT 26 +10V
REF
CALIBRATION DAC
15 SOUT
24 SPAN/
BIP
OFF
23 VOUT
27 MUXOUT
28 MUXIN
22 AGND
TRANSFER STD DAC
CALIBRATION SEQUENCER
1
CALOK
2
CAL
3
–VEE
4
+VCC
5
+VLL
6
DGND
Figure 2. Functional Block Diagram
In the first step of DNL calibration the output of the MAIN
DAC is set to the code just below the code to be calibrated.
The extra LSB in the MAIN DAC is turned on to find the ex-
trapolated value for the next code. The comparator is then
nulled using TRANSFER STD DAC. The voltage at VOUT
has in effect been sampled at the code to be calibrated.
Next, the extra LSB is turned off and the MAIN DAC code is
incremented by one LSB. The comparator is once again
nulled, this time with the CALDAC, until the VOUT is adjusted
to equal the previously sampled output. The CALDAC code is
stored in RAM and the process is repeated for the next code.
–6– REV. A

6 Page









AD760 pdf, datenblatt
AD760
One feature that the AD760 incorporates to help the user layout
is that the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/
BIP OFFSET, VOUT, MUXOUT, MUXIN and AGND) are adja-
cent to help isolate analog signals from digital signals.
SUPPLY DECOUPLING
The AD760 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 µF tantalum
capacitor in parallel with a 0.1 µF ceramic capacitor provides ad-
equate decoupling. VCC and VEE should be bypassed to analog
ground, while VLL should be decoupled to digital ground.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD760, associated analog circuitry and interconnections as
far as possible from logic circuitry. A solid analog ground plane
around the AD760 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction is not
recommended; careful printed circuit construction is preferred.
GROUNDING
The AD760 has two pins, designated analog ground (AGND)
and digital ground (DGND.) The analog ground pin is the
“high quality” ground reference point for the device. Any exter-
nal loads on the output of the AD760 should be returned to
analog ground. If an external reference is used, this should also
be returned to the analog ground.
If a single AD760 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD760. If multiple AD760s are used or the AD760 shares ana-
log supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
PACKAGE INFORMATION
28-Pin Cerdip Package (Q-28)
1.490 (37.84) MAX
28
1
GLASS SEALANT
15
0.525 (13.33)
0.515 (13.08)
14
0.125 (3.175)
MIN
0.620 (15.74)
0.590 (14.93)
0.22
(5.59)
MAX
0.02 (0.5)
0.016 (0.406)
0.11 (2.79)
0.099 (2.28)
0.06 (1.52)
0.05 (1.27)
0.012 (0.305)
0.008 (0.203)
15°
0°
0.18 (4.57)
MAX
–12–
REV. A

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