PDF AD9742 Data sheet ( Hoja de datos )

Número de pieza	AD9742
Descripción	TxDAC Digital-to-Analog Converter
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet 12-Bit, 210 MSPS TxDAC Digital-to-Analog Converter AD9742 FEATURES High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR at 5 MHz output, 125 MSPS: 70 dB Twos complement or straight binary data format Differential current outputs: 2 mA to 20 mA Power dissipation: 135 mW at 3.3 V Power-down mode: 15 mW at 3.3 V On-chip 1.2 V Reference CMOS compatible digital interface 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP Edge-triggered latches APPLICATIONS Wideband communication transmit channel: Direct IF Base stations Wireless local loops Digital radio links Direct digital synthesis (DDS) Instrumentation GENERAL DESCRIPTION The AD97421 is a 12-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9742 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9742’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. 1 Protected by U.S. Patent Numbers: 5,568,145; 5,689,257; and 5,703,519. FUNCTIONAL BLOCK DIAGRAM 3.3V 0.1µF RSET 3.3V CLOCK REFLO 1.2V REF REFIO FS ADJ 150pF AVDD ACOM CURRENT AD9742 SOURCE ARRAY DVDD DCOM SEGMENTED SWITCHES LSB SWITCHES IOUTA IOUTB CLOCK LATCHES MODE SLEEP DIGITAL DATA INPUTS (DB11–DB0) Figure 1. Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS 1. The AD9742 is the 12-bit member of the pin-compatible TxDAC family, which offers excellent INL and DNL performance. 2. Data input supports twos complement or straight binary data coding. 3. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. 4. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full- scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. On-chip voltage reference: The AD9742 includes a 1.2 V temperature compensated band gap voltage reference. 6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD9742 Data Sheet DYNAMIC SPECIFICATIONS TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA)2 Output Noise (IOUTFS = 2 mA)2 Noise Spectral Density3 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 25 MSPS; fOUT = 1.00 MHz 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output fCLOCK = 65 MSPS; fOUT = 1.00 MHz fCLOCK = 65 MSPS; fOUT = 2.51 MHz fCLOCK = 65 MSPS; fOUT = 10 MHz fCLOCK = 65 MSPS; fOUT = 15 MHz fCLOCK = 65 MSPS; fOUT = 25 MHz fCLOCK = 165 MSPS; fOUT = 21 MHz fCLOCK = 165 MSPS; fOUT = 41 MHz fCLOCK = 210 MSPS; fOUT = 40 MHz fCLOCK = 210 MSPS; fOUT = 69 MHz Spurious-Free Dynamic Range within a Window fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span fCLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 25 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 2.00 MHz fCLOCK = 65 MSPS; fOUT = 2.00 MHz fCLOCK = 125 MSPS; fOUT = 2.00 MHz Signal-to-Noise Ratio fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA fCLOCK = 210 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA Min Typ Max Unit 210 11 1 5 2.5 2.5 50 30 −152 MSPS ns ns pV-sec ns ns pA/√Hz pA/√Hz dBm/Hz 74 84 85 82 76 85 83 80 75 74 72 60 67 60 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 80 90 90 90 dBc dBc dBc dBc −82 −74 dBc −77 dBc −77 dBc −77 dBc 78 dB 86 dB 73 dB 78 dB 69 dB 71 dB 69 dB 66 dB Rev. C \| Page 4 of 32 5 Page AD9742 90 85 4MHz 80 75 19MHz 70 65 49MHz 60 55 34MHz 50 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 17. SFDR vs. Temperature @ 165 MSPS, 0 dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1 fCLOCK = 78MSPS fOUT = 15.0MHz SFDR = 79dBc AMPLITUDE = 0dBFS 6 11 16 21 26 31 36 FREQUENCY (MHz) Figure 18. Single-Tone SFDR Data Sheet 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1 fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz SFDR = 77dBc AMPLITUDE = 0dBFS 6 11 16 21 26 31 36 FREQUENCY (MHz) Figure 19. Dual-Tone SFDR 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1 fCLOCK = 78MSPS fOUT1 = 15.0MHz fOUT2 = 15.4MHz fOUT3 = 15.8MHz fOUT4 = 16.2MHz SFDR = 75dBc AMPLITUDE = 0dBFS 6 11 16 21 26 31 36 FREQUENCY (MHz) Figure 20. Four-Tone SFDR 3.3V 0.1µF VREFIO RSET 2kΩ CLOCK IREF 3.3V REFLO 1.2V REF REFIO FS ADJ 150pF AVDD ACOM AD9742 PMOS CURRENT SOURCE ARRAY DVDD DCOM SEGMENTED SWITCHES FOR DB11–DB3 LSB SWITCHES IOUTA IOUTB CLOCK SLEEP LATCHES VDIFF = VOUTA – VOUTB IOUTA IOUTB VOUTB MODE RLOAD 50Ω VOUTA RLOAD 50Ω DIGITAL DATA INPUTS (DB11–DB0) Figure 21. Simplified Block Diagram (SOIC/TSSOP Packages) Rev. C \| Page 10 of 32 11 Page

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