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AD9221 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9221
Beschreibung Monolithic A/D Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9221 Datasheet, Funktion
Complete 12-Bit 1.5/3.0/10.0 MSPS
Monolithic A/D Converters
AD9221/AD9223/AD9220
FEATURES
Monolithic 12-Bit A/D Converter Product Family
Family Members Are: AD9221, AD9223, and AD9220
Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and
10.0 MSPS
Low Power Dissipation: 59 mW, 100 mW, and 250 mW
Single 5 V Supply
Integral Nonlinearity Error: 0.5 LSB
Differential Nonlinearity Error: 0.3 LSB
Input Referred Noise: 0.09 LSB
Complete On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 70 dB
Spurious-Free Dynamic Range: 86 dB
Out-of-Range Indicator
Straight Binary Output Data
28-Lead SOIC and 28-Lead SSOP
GENERAL DESCRIPTION
The AD9221, AD9223, and AD9220 are a generation of high
performance, single supply 12-bit analog-to-digital converters.
Each device exhibits true 12-bit linearity and temperature drift
performance1 as well as 11.5-bit or better ac performance.2 The
AD9221/AD9223/AD9220 share the same interface options,
package, and pinout. Thus, the product family provides an upward
or downward component selection path based on performance,
sample rate and power. The devices differ with respect to their
specified sampling rate, and power consumption, which is reflected
in their dynamic performance over frequency.
The AD9221/AD9223/AD9220 combine a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid and monolithic implementations at
a fraction of the power consumption and cost. Each device is a
complete, monolithic ADC with an on-chip, high performance,
low noise sample-and-hold amplifier and programmable voltage
reference. An external reference can also be chosen to suit the
dc accuracy and temperature drift requirements of the application.
The devices use a multistage differential pipelined architecture
with digital output error correction logic to provide 12-bit accu-
racy at the specified data rates and to guarantee no missing
codes over the full operating temperature range.
The input of the AD9221/AD9223/AD9220 is highly flexible,
allowing for easy interfacing to imaging, communications, medi-
cal, and data-acquisition systems. A truly differential input
structure allows for both single-ended and differential input
interfaces of varying input spans. The sample-and-hold
NOTES
1Excluding internal voltage reference.
2Depends on the analog input configuration.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DVDD
VINA
VINB
CAPT
CAPB
VREF
SENSE
SHA
MDAC1
GAIN = 16
MDAC2
GAIN = 8
MDAC3
GAIN = 4
5
A/D
4
A/D
3
A/D
54
3
DIGITAL CORRECTION LOGIC
12
OUTPUT BUFFERS
A/D
3
MODE
SELECT
1V
AD9221/AD9223/AD9220
REFCOM
AVSS
DVSS
CML
OTR
BIT 1
(MSB)
BIT 12
(LSB)
amplifier (SHA) is equally suited for both multiplexed sys-
tems that switch full-scale voltage levels in successive channels
as well as sampling single-channel inputs at frequencies up to
and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220
is well suited for communication systems employing Direct-
IF down conversion since the SHA in the differential input
mode can achieve excellent dynamic performance far beyond its
specified Nyquist frequency.2
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over-
flow condition that can be used with the most significant bit to
determine low or high overflow.
PRODUCT HIGHLIGHTS
The AD9221/AD9223/AD9220 family offers a complete single-
chip sampling 12-bit, analog-to-digital conversion function in
pin compatible 28-lead SOIC and SSOP packages.
Flexible Sampling Rates—The AD9221, AD9223, and AD9220
offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS,
respectively.
Low Power and Single Supply—The AD9221, AD9223, and
AD9220 consume only 59 mW, 100 mW, and 250 mW, respec-
tively, on a single 5 V power supply.
Excellent DC Performance Over Temperature—The AD9221/
AD9223/AD9220 provide 12-bit linearity and temperature drift
performance.1
Excellent AC Performance and Low Noise—The AD9221/
AD9223/AD9220 provide better than 11.3 ENOB performance
and have an input referred noise of 0.09 LSB rms.2
Flexible Analog Input Range—The versatile on-board sample-
and-hold (SHA) can be configured for either single-ended or
differential inputs of varying input spans.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD9221 Datasheet, Funktion
AD9221/AD9223/AD9220
AD9221–Typical Performance Characteristics (AVDD = 5 V, DVDD = 5 V, fSAMPLE = 1.5 MSPS, TA = 25؇C)
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
CODE
4095
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
CODE
4095
8,180,388
121,764
N–1 N
CODE
85,895
N+1
TPC 1. Typical DNL
TPC 2. Typical INL
TPC 3. “Grounded-Input”
Histogram (Input Span = 2 V p-p)
80
75
–0.5dB
70
65 –6.0dB
60
55
–20.0dB
50
45
40
0.1
1.0
FREQUENCY – MHz
TPC 4. SINAD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.1
–20.0dB
–6.0dB
–0.5dB
1.0
FREQUENCY – MHz
TPC 5. THD vs. Input Frequency
(Input Span = 2.0 V p-p, VCM = 2.5 V)
80
75 –0.5dB
70
65 –6.0dB
60
55 –20.0dB
50
45
40
0.1
1.0
FREQUENCY – MHz
TPC 6. SINAD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
–50
–55
–20.0dB
–60
–65
–70
–0.5dB
–75
–6.0dB
–80
–85
–90
0.1
1.0
FREQUENCY – MHz
TPC 7. THD vs. Input Frequency
(Input Span = 5.0 V p-p, VCM = 2.5 V)
–60
–65
–70
–75
–80 5V p-p
–85
2V p-p
–90
–95
–100
0.2 0.3 0.4 0.6 0.8 1
2
SAMPLE RATE – MSPS
TPC 8. THD vs. Sample Rate
(AIN = –0.5 dB, fIN = 500 kHz,
VCM = 2.5 V)
3
100
90
80
70
SFDR
60
50
SNR
40
30
20
10
–60 –50
–40 –30 –20
AIN – dBFS
–10
0
TPC 9. SNR/SFDR vs. AIN (Input
Amplitude) (fIN = 500 kHz, Input
Span = 2 V p-p, VCM = 2.5 V)
–6– REV. E

6 Page









AD9221 pdf, datenblatt
AD9221/AD9223/AD9220
shunt capacitor can help limit the wideband noise at the A/D’s
input by forming a low-pass filter. Note, however, that the
combination of this series resistance with the equivalent input
capacitance of the AD9221/AD9223/AD9220 should be evalu-
ated for those time-domain applications that are sensitive to the
input signal’s absolute settling time. In applications where har-
monic distortion is not a primary concern, the series resistance
may be selected in combination with the SHA’s nominal 16 pF of
input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e., VINA
and/or VINB) and analog ground. Since this additional shunt
capacitance combines with the equivalent input capacitance of
the AD9221/AD9223/AD9220, a lower series resistance can
be selected to establish the filter’s cutoff frequency while not
degrading the distortion performance of the device. The shunt
capacitance also acts like a charge reservoir, sinking or sourcing
the additional charge required by the hold capacitor, CH, further
reducing current transients seen at the op amp’s output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9221/AD9223/AD9220 should be evaluated. To
optimize performance when noise is the primary consideration,
increase the shunt capacitance as much as the transient response
of the input signal will allow. Increasing the capacitance too
much may adversely affect the op amp’s settling time, frequency
response, and distortion performance.
REFERENCE OPERATION
The AD9221/AD9223/AD9220 contain an on-board band gap
reference that provides a pin-strappable option to generate
either a 1 V or 2.5 V output. With the addition of two external
resistors, the user can generate reference voltages other than 1 V
and 2.5 V. Another alternative is to use an external reference for
designs requiring enhanced accuracy and/or drift performance.
See Table II for a summary of the pin-strapping options for the
AD9221/AD9223/AD9220 reference configurations.
Figure 9 shows a simplified model of the internal voltage reference
of the AD9221/AD9223/AD9220. A pin-strappable reference
amplifier buffers a 1 V fixed reference. The output from the
reference amplifier, A1, appears on the VREF pin. The voltage
on the VREF pin determines the full-scale input span of the
A/D. This input span equals,
Full-Scale Input Span = 2 ϫ VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators that monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path
of A1. If the SENSE pin is tied to REFCOM, the switch is
connected to the internal resistor network, thus providing a
VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a
short or resistor, the switch is connected to the SENSE pin. A
short will provide a VREF of 1.0 V while an external resistor
network will provide an alternative VREF between 1.0 V and
2.5 V. The other comparator controls internal circuitry that will
disable the reference amplifier if the SENSE pin is tied to AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
AD9221/AD9223/AD9220
TO
A/D
5k
5k
A2
5k
DISABLE
A2
5k
LOGIC
CAPT
CAPB
A1
1V
VREF
7.5k
DISABLE
A1
LOGIC
5k
SENSE
REFCOM
Figure 9. Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9221/AD9223/AD9220 appear on the CAPT and CAPB
pins. For proper operation when using the internal or an external
reference, it is necessary to add a capacitor network to decouple
these pins. Figure 10 shows the recommended decoupling net-
work. This capacitive network performs the following three
functions: (1) along with the reference amplifier, A2, it provides
a low source impedance over a large frequency range to drive
the A/D internal circuitry, (2) it provides the necessary compen-
sation for A2, and (3) it band-limits the noise contribution from
the reference. The turn-on time of the reference voltage appear-
ing between CAPT and CAPB is approximately 15 ms and
should be evaluated in any power-down mode of operation.
CAPT
AD9221/
AD9223/
AD9220
CAPB
0.1F
0.1F
10F
0.1F
Figure 10. Recommended CAPT/CAPB Decoupling
Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM, and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4, respec-
tively, in which the input span can be varied between 2 V and
5 V. Note that those samples within the pipeline A/D during
any reference transition will be corrupted and should be
discarded.
–12–
REV. E

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